[time-nuts] Gate propagation delay jitter

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Apr 10 06:32:47 EDT 2007


Ulrich Bangert wrote:
> Bruce,
>
> the following is part of a discussion in comp.arch.fpga:
>
> ........................................................................
> .
> Hi, 
> I would like to know what are the common methods of introducing 
> delays as low as 10ps between two outputs in an FPGA. I do not 
> currently have a specific FPGA in mind. I am just looking for a 
> general answer. 
>
>  I know there are DCMs but this usually adds jitter and one needs to 
> wait for the DCM output to phase lock before the signal is stable and 
> it might take too long in our case. Basically I would want to power up 
> a board and have the delay be set in as short a time as possible. I 
> also need to minimise jitter to a minimum so that the two signals are 
> NEVER high at the same time. Thanks for any answer. 
> Amish 
> ........................................................................
> ..
> Amish, 
> The only method I am aware of is hand routing.  10ps is too small to 
> really be able to hold to in all cases.  With 35ps p-p jitter (minimum) 
> in any FPGA, and +/- 10 ps route matching (due to process variations 
> chip to chip), this may be impossible. 
> Austin (Leesa)
> ........................................................................
> ..
> Austin, 
>   
>> With 35ps p-p jitter (minimum) in any FPGA... 
>>     
> I am currently designing some circuitry that needs to have jitter as low
> as 
> possible, therefore this spec is most interesting for me. Are you
> talking 
> about jitter introduced by DCMs or does ANY logic contained in an FPGA 
> exhibit this jitter even when clocked with a low jitter clock. I have a
> 0.8 
> ps RMS jitter clock source available (DS4077). If the logic that I would
>
> like to clock with it would make a 35 ps pp minimum jitter out of it
> this 
> would be a sheer catastrophe for me! 
> Best regards 
> Ulrich Bangert 
> ........................................................................
> ..
> Ulrich, 
> Just go into any CMOS chip, and then immediately leave that chip. 
> That is 35 ps right there (a 74AHC04 for example). 
> If you use LVDS, and have perfect terminations, maybe it becomes 25 ps. 
> Call it a limitation of the technology of bulk CMOS. 
> If you do anything else, the number just gets bigger. 
> If you anything wrong, the number also gets bigger (bad bypassing, bad 
> SI, etc.) 
> Austin (Leesa)
> ........................................................................
> ..
>
> Austin Leesa's opinion is in heavy contrast to your table but he is a
> very experienced man. So, whom to believe?
>
> Best regards
> Ulrich Bangert
>   
Ulrich

The table was snipped from an Analog Devices application note (AN501).
The ECL jitter is consistent with what I would expect.
However the CMOS jitter, particularly for HCMOS is about 10x less than I 
would have expected.
Which is why I would like to find another technique to measure it.
If its around 25 ps RMS or more than it can probably be done with an HP5370.
It is just possible a decimal point was misplaced.
However we need to be certain everyone is using the same jitter measure 
ie. RMS.
Also need to know what the measurement bandwidth is.
Austins figures seem OK for HCMOS but somewhat too high for ACMOS.

Since there are commercial CMOS output crystal oscillators with 25ps 
jitter, the jitter of CMOS devices (at least at room temperature) can be 
a little better than 35ps.

Also there a CMOS TDCs with a jitter considerably better than 10ps.

The jitter quoted is presumably for a very low jitter fast risetime source.
Thus the input noise of the gate has no effect on the output jitter 
because the input signal slew rate is too high.
Only the intrinsic jitter of the gate is effective.

It would be nice to have a reliable set of figures for the jitter of 
CMOS devices (ECL jitter is somewhat more difficult to measure).

In principle one could use a chain of inverters and use a time interval 
counter or other technique to measure the statistics of the propagation 
delay of a single gate near the end of the chain where the input slew 
rate is as high as its going to be.

In principle its probably just possible to build a relatively 
inexpensive analog (current source + capacitor plus schottky diodes and 
an ADC) circuit that can actually measure sub picosecond jitter. It is 
certainly very easy if its done on an SiGe chip, but the current limits 
of discrete construction are a little uncertain. It may be possible with 
8GHz transistor arrays.

I await Bob Paddock's circuit with bated breath.


Bruce





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