[time-nuts] Gate propagation delay jitter
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Tue Apr 10 21:27:32 UTC 2007
Enrico Rubiola wrote:
> My friends, if you worry about jitter there is a trick:
> synchronize the signat to the clock with a D-type flip flop,
> just at the output.
> Maybe too trivial for you.
> E.
>
>
> Enrico Rubiola
> professor of electronics
>
> web: http://rubiola.org
> e-mail: rubiola at femto-st.fr
>
> FEMTO-ST Institute
> 32 av. de l'Observatoire
> 25044 Besancon, FRANCE
> voice: +33(0)381.853940 (E.Rubiola)
> voice: +33(0)381.853999 (switchboard)
> fax: +33(0)381.853998
>
>
> _______________________________________________
> time-nuts mailing list
> time-nuts at febo.com
> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>
>
Enrico
Then we would need to know/measure the jitter of the retiming flipflop.
There appears to be little definitive published data on the jitter of
various logic gates and flipflops.
Consequently a simple reliable method of measuring such jitter would be
useful.
Bruce
More information about the Time-nuts_lists.febo.com
mailing list