[time-nuts] Gate propagation delay jitter
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Tue Apr 10 17:27:32 EDT 2007
Enrico Rubiola wrote:
> My friends, if you worry about jitter there is a trick:
> synchronize the signat to the clock with a D-type flip flop,
> just at the output.
> Maybe too trivial for you.
> Enrico Rubiola
> professor of electronics
> web: http://rubiola.org
> e-mail: rubiola at femto-st.fr
> FEMTO-ST Institute
> 32 av. de l'Observatoire
> 25044 Besancon, FRANCE
> voice: +33(0)381.853940 (E.Rubiola)
> voice: +33(0)381.853999 (switchboard)
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Then we would need to know/measure the jitter of the retiming flipflop.
There appears to be little definitive published data on the jitter of
various logic gates and flipflops.
Consequently a simple reliable method of measuring such jitter would be
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