[time-nuts] Gate propagation delay jitter

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Apr 10 20:04:02 EDT 2007


SAIDJACK at aol.com wrote:
>  
> In a message dated 4/10/2007 14:33:17 Pacific Daylight Time,  
> bruce.griffiths at xtra.co.nz writes:
>
> Yes  ground bounce can play havoc with the effective switching thresholds.
> One  would expect this effect to be much worse with single ended  clocks.
>
> Bruce
>
>
>
> Hi Bruce,
>  
> not to give away too much, but in our Jackson-Labs Fury GPSDO we  compensate 
> for VDD bounce as well by having fully-differential circuits with  special 
> current balancing circuitry.
>  
> Thus not only do clocks have to be differential, but every output of the  
> circuit should be differential as well to balance the VDD currents.
>  
> This helps prevent feeding noise into the VDD rails, which can show up at  
> other IC's. We were able to completely get rid of spurs in our phase noise  
> measurements with this technique.
>  
> bye,
> Said 
>
>
>
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>   
Said

Yes differential input and output current mode logic with balanced loads 
works very well with low power supply noise coupling.

Bruce




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