[time-nuts] Of rubidium life and piggy-bank anemia....

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat Dec 1 23:42:52 UTC 2007


Hal Murray wrote:
>> Bad idea, you should only be using a single counter with perhaps
>> multiple registers to save the count. However a using a single address
>> and a FIFO can save significant time when using a microprocessor to
>> read/process the stored counter samples. 
>>     
>
> I think we may be looking at two different problems.
>
> Your approach makes sense when looking at PPS signals.
>
> I was thinking of looking at several 10 MHz signals.
>
> It would be easy to convert 10 MHz to a PPS signal with a big divider.  (Some 
> other scale factor may be more convenient.)
>
> I was just going to count cycles.  No good reason, but it seemed easy to do 
> and I thought/hoped it had enough information to be useful.
>
>
> I was assuming the FPGA had a 100 MHz clock - anything significantly faster 
> than the signal you are looking at.  First run the 10 MHz signals through a 
> synchronizer.  Then bump a counter on each rising edge.
>
> Another signal would grab copies of all the counters.  That could be either a 
> poke from a PC or something handy like a PPS signal.  The PC would then read 
> the counters.
>
> If the PC does the poke, there are no timing requirements.  If the PC is slow 
> you may not get what you wanted, but the data within each sample will be 
> consistent.
>
> If you do the poke with a PPS, you probably want another register that counts 
> pokes.  The PC can then read it at the beginning and end of grabbing the 
> data.  If the two copies are different you had timing troubles.  Dump that 
> sample.  Comparing the poke-count between samples tells you when you missed 
> some samples.
>
> I was thinking of "grab" as PCI reads.  You could also send the samples out 
> over RS232.  (A checksum on the line seems like a good idea.)
>
>
>
>
>
>   
There seems to be little point to this approach, neither NIST nor JPL
use anything like this.
This technique also has the undesirable side effect of increasing the
synchroniser failure rate significantly.

In most cases sampling the 10Mhz source phase every second or so (at the
output of a PPS divider) is more than adequate for evaluating its
stability over time intervals of 1 s or more.
Your technique will not allow the phase variations of the 10MHz signals
to be easily determined.

The conventional approach adopted by NIST is to divide each frequency to
be measured down to 1 PPS, then timestamp the PPS transitions for each
channel as well as the PPS transitions from a GPS timing receiver. By
using the same setup at NIST with their frequency standards most of the
noise due to ionospheric delay variations is a common to both systems
and is eliminated on subtraction.

Bruce




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