[time-nuts] is there a "best bet" advanced hobbyist buildable GPSDOdesign?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Wed Dec 12 11:07:58 UTC 2007


Luis Cupido wrote:
> Hi Bruce,
>
>
> Fine, you don't like the words "far better performance"... okay ;-)
> you do recognize the small advantage in noise but
> gave no relevance to the other aspects namely the
> lock acquisition, the fact that I can monitor the jitter over time
> etc. (all of them were contained in my word "performance"
> not just the noise).
>   
Its not too difficult to add a couple of extra flipflops plus associated
delays to allow reasonably accurate estimation of noise if thats useful.
> you wrote,
>  > By all means try them,
>
> Humm?! I did tried them, that's exactly what I said !!!
> Note that I do have the hardware on a CPLD so schemes
> can be done on type-compile-and-test basis without
> soldering wires hi ;-)
>
>   
A theoretical understanding the performance tradeoffs can save a lot of
time and effort.
>  > but why add the power consumption and complexity
>  > of a CPLD if it offers little improvement in performance?
>
> Geeee, using a CPLD does not add complexity, it is just one chip
> and it offers the commodity of being easily configured etc.
> Also the power consumption is surely not an issue, if you
> are not happy with the 50 to 100mA you may draw from 3.3v
> just use a low power CPLD (like tha maxIIZ) and get
> only 10 to 20mA.
>
>   
You have to keep in mind that not everyone on this list can or wants to
program a CPLD.
> On the comments about the filter and bandwidth I do agree
> with you it would be good to have most of it digital
> (doesn't need to be necessarily on a CPU... inside the CPLD
> is the same) I do have versions with integration also
> in digital and I'm still in the process of improving it.
> I believe I may get rid off of some of the inconvenient
> analog filtering, in the next VHDL iterations hi ;-)
>
>
> One thing is puzzling me, if you suggest using a
> single D flip-flop and want it simple as you say
> I presume you have also to filter in analog ?!
>   
Where did you get that from??
No analog filtering of the D flipflop output is required.
> So you end up with a slightly worst phase comparator
> and the less convenient analog filter :-(
>   
Try reading up on how the radio astronomers digitise their noise like
signals.
You should also look at why a 1-2 bit ADC suffices for most GPS timing
receivers.
> Or do you need to add a microcontroller and a DAC ?
> If that is the case, there goes off your complexity issue
> much higher than a simple CPLD.
>
>   
I've used plenty of CPLDs but see no reason to use one when it isnt
necessary.
If you want really high phase measurement resolution then the high noise
internal environment of a CPLD can add plenty of jitter and unwanted
crosstalk.
You are unlikely to ever achieve a jitter of 10picosec or less with a
standard CPLD whereas this is readily achieved using a single flipflop
or a wideband ADC used as a phase detector.
> Luis Cupido.
> ct1dmk
>
>   
Bruce




More information about the Time-nuts_lists.febo.com mailing list