[time-nuts] Locking 100 MHz to 10 MHz

[John Miles]

> A good spectrum analyzer (such as HP 8560B/E etc with the phase-noise
> software option) should allow you to measure <-68dBc/Hz noise at
> 100Hz offset  at
> 100MHz, so you can check what BW results in the overall lowest noise.

True, the specs on that 100 MHz VCXO are not what you'd call high-end.
Pretty much any decent SA will measure its noise directly between 100 Hz and
1 kHz.  An 8568A/B running my phase-noise app will do it for about 1/4 the
cost of an 8560E.

With a noisy VCXO like that, I would certainly favor wider loop bandwidths
over narrower ones.  1 kHz would be the minimum I'd consider using.
Anyone using an external 10 MHz clock is probably getting it from something
like a Thunderbolt, Z3801, or homebrew GPS clock with a decent 10 MHz OCXO.

Count on the external 10 MHz clock coming in at -135 dBc/Hz or better at 1
kHz, IMO, which when scaled to 100 MHz becomes -115 dBc/Hz at 1 kHz.  Your
VCXO is at -98 there, so it will certainly benefit from a loop bandwidth
that wide.  By 10 kHz, though, your VCXO is as clean as a 10811A scaled to
100 MHz.  So I wouldn't go much wider than 3-5 kHz under any conditions, for
fear of letting a lower-quality 10 MHz source make things worse.

Do not use a 50K resistor at your charge-pump output, though!  That will
cause the PLL to 'hunt' continually, adding reference sidebands to the
output.  I would use a JFET or CMOS analog switch, or even a relay, to
disconnect the charge pump and switch in the half-rail fixed supply.

-- john, KE5FX