[time-nuts] Locking 100 MHz to 10 MHz

Matt Ettus boyscout at gmail.com
Wed Dec 19 20:56:17 UTC 2007


On Dec 19, 2007 12:06 PM, John Miles <jmiles at pop.net> wrote:
>
> > A good spectrum analyzer (such as HP 8560B/E etc with the phase-noise
> > software option) should allow you to measure <-68dBc/Hz noise at
> > 100Hz offset  at
> > 100MHz, so you can check what BW results in the overall lowest noise.
>
> True, the specs on that 100 MHz VCXO are not what you'd call high-end.
> Pretty much any decent SA will measure its noise directly between 100 Hz and
> 1 kHz.  An 8568A/B running my phase-noise app will do it for about 1/4 the
> cost of an 8560E.
>
> With a noisy VCXO like that, I would certainly favor wider loop bandwidths
> over narrower ones.  1 kHz would be the minimum I'd consider using.
> Anyone using an external 10 MHz clock is probably getting it from something
> like a Thunderbolt, Z3801, or homebrew GPS clock with a decent 10 MHz OCXO.
>
> Count on the external 10 MHz clock coming in at -135 dBc/Hz or better at 1
> kHz, IMO, which when scaled to 100 MHz becomes -115 dBc/Hz at 1 kHz.  Your
> VCXO is at -98 there, so it will certainly benefit from a loop bandwidth
> that wide.  By 10 kHz, though, your VCXO is as clean as a 10811A scaled to
> 100 MHz.  So I wouldn't go much wider than 3-5 kHz under any conditions, for
> fear of letting a lower-quality 10 MHz source make things worse.

That is good information.  My other fear is that the user's 10 MHz
will pick up some 60 Hz on the way to my system, but I suppose there
is no way I want to be narrower than 60 Hz on my loop bandwidth.

> Do not use a 50K resistor at your charge-pump output, though!  That will
> cause the PLL to 'hunt' continually, adding reference sidebands to the
> output.  I would use a JFET or CMOS analog switch, or even a relay, to
> disconnect the charge pump and switch in the half-rail fixed supply.

That is what I was afraid of.  Thanks for the warning.

Matt




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