[time-nuts] Austron PRR-10 GPS discliplined Rb...

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Mon Jan 29 08:57:26 UTC 2007


Hal Murray wrote:
>> 	Of course for phase comparison with the input, one actually does not
>> need much filtering as one is only using the NCO digital output as an
>> input to a phase comparator... spurs and so forth don't count at all
>> here as they get filtered out in the subsequent loop filter for the
>> PLL (which is very narrow). 
>>     
>
> I don't understand this area well enough.  Can somebody give me a few (more) 
> hints?
>
> Are we talking analog filters in hardware or software filters in a small CPU?
>
> How narrow an analog filter can I purchase or make?  (at reasonable price or 
> board space or design time or whatever)
>
> How close do the spurs get?  I thought they got quite close if the DDS 
> parameters were close to a good frequency.  Do they get smaller as they get 
> closer, or something convenient like that?
>
> What's the term for the set of frequencies that a DDS can make with no spurs? 
>  Say with a divide by 8.  I'm guessing that the criteria for that is 
> something like
> no bits left on in the low bits when the carry out of the low bits happens.  
> By low bits I mean the ones the A/D doesn't see.
>
>
>   
>> I presume that the leading edge of the GPS receiver PPS pulse samples
>> the DDS phase accumulator register content. 
>>     
>
> That would be easy if the DDS were built in an FPGA.  (There is the 
> synchronizer delay to complicate things, but that and other pipeline stages 
> are just a constant offset.)
>
>
>
>   
Hal

The synchroniser delay isn't constant it changes from one PPS pulse to 
the next. The synchroniser delay variation has a peak to peak amplitude 
of about 2 synchroniser clock periods. You can minimise it by increasing 
the clock speed or you can measure the synchroniser delay for each PPS 
pulse with a TDC.

It is generally impractical to implement a very narrow PLL filter with 
analog components, it has to be done in hardware, either dedicated 
hardware or a processor with associated firmware.

A phase lock loop time constant of up to a few seconds isn't too 
difficult to implement with analog components.

With an unfortunate choice of frequency spurs can get very close indeed.

There are several causes of spurs including:

1) DAC nonlinearities and glitches- these are created by the DAC and do 
not exist in the DAC digital data input sequence.

2) Phase truncation

Spur frequencies are predictable, they have a constant frequency for any 
given frequency tuning word the relative phase of the spur is fixed and 
the amplitude changes somewhat with process variables, temperature, 
supply voltage.
Consequently it is possible to null out any given spur by predistorting 
the digital input to the DAC or by using analog cancellation techniques.

Spurs vanish when the generated frequency is a subharmonic (the DDS 
clock frequency is a harmonic of the DDS output frequency) of the DDS 
clock frequency.
Filtering spurs is less problematic if the DDS output frequency is less 
than 1/3 of the DDS clock frequency.

If one is correcting the frequency of a standard then spurs will always 
be present to some extent in the DDS output.
One way of cleaning these spurs up in the analog domain is to phase lock 
a VCXO with good short term stability to the DDS output with a narrrow 
bandwidth phase lock loop. Another way is to use a divider to reduce the 
spur amplitude by 6dB every time the DDS output is divided by 2.
The cascaded mix and divide technique quickly reduces the spur amplitude 
to the system noise level if suitable dividers, mixers, amplifiers and 
filters are used particularly in the last mixer divider stage.

Bruce





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