[time-nuts] Low noise frequency multiplication

[SAIDJACK at aol.com]

In a message dated 2/28/2007 15:20:56 Pacific Standard Time,  
stephan at rrsg.ee.uct.ac.za writes:

It  describes a way in which an analogue odd-order frequency multiplier  could
be built cheaply with superior noise characteristics. This circuit  that is
described is really simple and quite ingenious. Unfortunately, I  would like
to multiply by 10 (an even number) so I still need a way to at  least
multiply by 2. Commercial low-noise multipliers are in general much  more
expensive than my OCXO. So now I am curious if there is an easy and  reliable
way to get a 10MHz sine up to 100MHz without degrading the phase  noise.



Hi Stephan,
 
one way to do it is using a DDS, say one of the new 1Gs/s 14-bit  DAC units 
from Analog Devices:
 
bring the 10MHz up to 1GHz using a 1 to 100 PLL and a low-phase noise 1GHz  
VCO or 1GHz crystal (these 1GHz low-jitter crystal Oscillators have  recently 
been advertised).
 
Then use the DDS to generate 100MHz at 1Gs/s.
 
Noise floors of <-155dBc/Hz can be easily achieved with a good DDS. You  will 
need is a low pass at around <400MHz to remove aliases etc.
 
One advantage of this is that you can generate essentially any frequency in  
<1Hz steps up to about 400MHz (without having a frequency-dependent  noise 
floor on the DDS output).
 
You could get a DDS eval board from Analog to do this. 
 
This is essentially what the Jackson-Labs FireFox Synthesizer  does.
 
bye,
Said
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