[time-nuts] Setting Osc Frequencies
Dr Bruce Griffiths
bruce.griffiths at xtra.co.nz
Sun Mar 4 00:23:11 UTC 2007
Tom
Attached schematic depicts an updated version of the digital part of the
K34-5991A.
Using LCX CMOS flipflops reduces the cost significantly, but the maximum
usable input frequency is also reduced, however operation to around
20MHz should be OK. The 2 stage synchroniser connected to the output of
flipflop U101:B minimises the effect of metastability in this flipflop.
The other 2 stage synchroniser is used to match the propagation delays
of both paths. CLKA and CLB can be produced by suitable clock shapers
(comparators with hysteresis??). The output of the exclusiveOR gate can
be low pass filtered, buffered, and level shifted by an opamp.
The digital circuit could also be implemented in a single fast low cost
programmable logic device.
If one wishes to compare the frequency of 2 nominally identical sources
that are within 1Hz or so of one another, then this simple circuit is a
low cost alternative to a time interval counter or equivalent device. As
long as one has a suitable relatively low resolution dc coupled ADC
(DVM???) connected to a computer the output can be easily logged.
Bruce
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