[time-nuts] Software Sawtooth correction prerequisites?

[Dr Bruce Griffiths]

The statement that Dallas' version of the nanosecond differs by 10% from 
Motorola's is somewhat disconcerting until one analyses how the delay 
generator works.
Simplified description

Aside from the contribution from internal logic propagation delays

Delay = Constant*RC,
Where R is the value of a resistor that determines the current used to 
charge a capacitor and the constant is determined by resistor ratios.

Thus a naive implementation may use 256 equal resistors (r) connected in 
series with a set of switches used to select the the required  
resistance value (Nr)  in 256 nominally equal steps.
The delay would then be proportional to N.
Unfortunately the ramp slope would vary over a range of 256 to 1 as 
would the current. The current mirror used in the actual circuit may 
have some dificulty in operating accurately over a current range of 
256:1. Also the power dissipation in some of the resistors in the string 
would vary over a large range. The large range (256:1) in the ramp slew 
rate seen by the comparator would lead to significant variations in the 
comparator delay. Fortunately if the effective value of the resistor 
corresponding to N=0 is made somewhat larger (=Ro) than r then although 
the N=0 delay will increased, the range of currents seen by the current 
mirror and the corresponding slew rates seen by the comparator can be 
reduced significantly improving the performance and reducing the 
variation in resistor dissipation. This implementation should be 
inherently monotonic despite variations in r and Ro. The effective RC 
product and the corresponding delay can be designed to have a low 
temperature coefficient. The RC product will vary from lot to lot and 
this variation can be compensated by resistor trimming. There are other 
schemes other than a series resistor string that can be used, however 
most of these are not inherently monotonic and resistor trimming to 
correct this error as well as the scale error may be necessary.

The attached plot of the error of a typical DS1020-15 illustrates that 
the integral non linearity of the delay may amount to several 
nanoseconds worst case.
This indicates that if one uses say 30ns of the range to correct for the 
sawtooth error of an M12M or equivalent GPS timing receiver, that a 
typical correction error due to the intergral non linearity of the 
DS1020-15 may be as large as 1ns. However this can be reduced 
significantly by calibration or perhaps by just calibrating the gain. 
However unless an actual calibration or parameter fitting to a more 
elaborate model for the INL other than just a change of scale factor the 
specified data sheet maximum value for the delay it is unlikely that a 
mere adjustment of the scale factor will ensure that the delay error of 
every DS1021-15 that meets its datasheet specification will be less than 
1 nanosecond. The optimum scale factor may also vary from wafer to wafer 
as well as within the wafer.

Thus whilst it is highly likely that calibrating the delay and using a 
lookup table or a model for the INL using several adjustable parameters 
will allow a programmed delay error of under 1ns, it is unlikely that 
merely adjusting the "gain" will reduce the programmed delay error to 
under 1ns for all DS1021-15s ever produced that meet the datasheet 
specifications.

More detailed
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