[time-nuts] Metastability?

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Sun May 20 18:15:48 EDT 2007

Hal Murray wrote:
>> You need to have a two stage register, allowing one clock period for
>> the first stage to come out of metastability.  This of course delays
>> the signal to be synchronized by a clock period.
> Yup.  The delay is unavoidable.  The only thing you can do is trade off delay 
> vs MTBF.
>> In an attempt to get around this delay, you sometimes see a series of
>> registers in cascade clocked at slightly different times in an attempt
>> to solve metastability w/o giving up a clock period.  This is unlikely
>> to work well.  You need one long settling period, not a bunch of short
>> ones.
> That's an example of the sort of bogus kludge I mentioned.
> Consider a chain of 3 FFs where the clock for the middle one is in between 
> the other two clocks.  Compare that to the same setup without the middle FF.
> In the first case, you have clock-out, setup, clock-out, and setup that gets 
> subtracted off from the settling time.  In the second case, you have 
> clock-out and setup that gets subtracted.  The extra setup/clock-out from the 
> middle FF is reducing the settling time.  Settling time is an exponential.  
> It's almost always wrong put anything in that path.
> It's not the number of FFs, it's the settling time that's important, or sum 
> of settling times.

Except that in synchronous systems where the the clock frequency is 
close to the worst case limit of the technology employed, it isn't 
always convenient or practical to wait longer than 1 clock period for 
the second flipflop to settle. In this case cascading chain of flipflops 
can be useful to reduce the probability of metastability at the output.
It would be better to use a slower synchroniser clock produced by 
dividing down the system clock for the synchroniser, but this may unduly 
constrain the maximum clock frequency when the delay between system 
clock transitions and the divided down clock transitions is considered, 
unless of course the divided down clock transitions are aligned with the 
system clock transitions.

With low frequency clocks (eg sampling/clocking with the leading edge of 
a PPS pulse) using a delay before sampling the output of the flipflop 
can be convenient in that it can be considerably shorter than the clock 
period whilst maintaining an acceptable MTBF.

If one connects the asynchronous signal to the inputs of a pair of 
synchronisers one of which is clocked by the rising edge of a clock and 
and the other by the falling edge of the same clock clock (~50% duty 
cycle), then one synchroniser will meet it setup and hold times 
(provided the clock frequency isn't too high) whilst the other may not. 
If the position of the asynchronous signal transition within the clock 
cycle were known then it would be possible to select the output from the 
synchroniser for which the input flipflop setup and hold times are met.  
Measuring the position of the asynchronous signal transition within the 
clock cycle introduces its own problems and the added complexity and 
cost isn't warranted except when one needs to timestamp the asynchronous 
signal transition with a resolution better than 1 clock cycle.

When using the traditional set of equations to calculate the MTBF of a 
synchroniser one has to be careful that the assumptions made in deriving 
these equations are valid for the particular case of interest.
An example of a synchroniser where these assumptions are violated is the 
case where a feedback loop is employed to lock the input signal 
transition so that  the output of the synchroniser has equal probability 
of being 1 or 0 when sampling this transition. In this case instead of 
having a uniform probability distribution of the location of the input 
signal transition within clock cycle, the location of such transitions 
has a narrow distribution about the sampling clock active transition. 
The "width" of the distribution being determined by the signal (or 
clock) jitter.

An example of this is when a D flipflop is used to lock an OCXO to the 
sawtooth corrected leading edge of the PPS pulse from a timing receiver.
The jitter on the sawtooth corrected PPS transition may then only be a 
few nanoseconds rms constraining that the PPS transition has a high 
probability of always being within a few nanoseconds of the OCXO derived 
clock transition. Thus although the sampling rate is very low it is 
essential to use a fast flipflop and/or wait long enough before sampling 
its output to achieve an adequately low synchroniser failure rate.


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