[time-nuts] 1Mhz to 1 PPS

[Bruce Griffiths]

Hal Murray wrote:
>> I would like to convert a 1 MHz sine wave to a 1 pps TTL.
>>     
>
> I'm assuming you aren't too concerned about jitter.
>
> There are two issues.  The first is converting your sine wave into a valid 
> logic level.  The second is dividing by a million.
>
> If your sine wave has a reasonable amplitude, I'd just feed it into a logic 
> gate.  If it's too big, I'd add a resistive divider.  You probably want to AC 
> couple the input.  That needs something to bias it at the right level.  A big 
> resistor from an inverted output usually works well.  It sets the bias point 
> to give you a 50-50 duty cycle.
>
>   
A Schmitt trigger device 74xx14 is generally better than a simple logic
gate.
CMOS Schmitt trigger devices are easier to rive than TTL type devices
especially if the source impedance is high.
> If you want to get fancy, use a comparator.
>
>
> For home construction, a row of 74HC390s is the best divider I can think of.  
> It gives you 2 divide by 10 stages in each package so you only need 3 chips.
>
>   
The jitter and clock to output delay (along with its tempco) is
increased when one cascades 390's.
Synchronously cascaded 160's have lower jitter and lower clock to output
delay.
> Are you tight for space?  Do you like low level software?  I'd probably do 
> the dividing in software on a PIC or AVR.  The 8 pin dips are easy to work 
> with but they come in tiny packages too.  They are usually setup to work with 
> a raw crystal or external clock.  You can probably find something that will 
> work with your sine wave.
>   
Resynchronising the divided output with a D flipflop will minimise clock
to output delay and associated jitter.
> Another alternative to a row of '390s is a CPLD or FPGA.  They usually only 
> come in packages with tiny pins which are hard for my old eyes to work with.  
> They might make sense if you need some logic for something else.
>
>
>   
FPGAs are nice but jitter can be high, resynchronising the divided
output with an external D flipflop will reduce this significantly.
You could also resynchronise the output of a 390 divider chain, however
the delay from clock in to output can be too large to reliably do this
in one step, when the input frequency is too high or the divider chain
too long.

Bruce