[time-nuts] 5 MHZ PIC PPS Divider?

[Stanley Reynolds]

Web articles on jitter:
http://www.maxim-ic.com/appnotes.cfm/an_pk/2744
http://www.pericom.com/pdf/applications/AB036.pdf
http://www.vectron.com/products/appnotes/jitter.htm
The last reference appears to have practical method to measure jitter in fig 5.
 
This is very detailed method but beyond my means:
http://www.cardinalxtal.com/docs/notes/jitter_paper.pdf
 
This may be closer but still expensive :
http://www.aubraux.com/dsp/jitter-software.php
 
Thinking out loud the adjustments of the GPS disciplined clocks such as Brooks Shera's has much of the same hardware, perhaps some modifications would allow jitter measurements from the ASCII status output ? Using the same device a PIC, to measure errors in PICs may not work. But perhaps a low cost way to measure the difference between the 10Mhz standard input and the PPS output and transferring this to a PC spreadsheet for analysis without the expensive test equipment ? I'm not thinking of using the exact same PIC to output the data of it's own, but a separate PIC to move the data to the PC. Also just the measurements needed not enough data to reproduce the whole waveform. The measuring PIC may need to buffer the Data to reduce the effects of slow speed transfer and any interaction of the transfer on the timing of the measurement.

What bothers me is actual measurment, quote from the cardinalxtal reference above :

"JITTER TESTING SET UP AND METHOD
Several factors must be considered when making jitter measurements.
• Use of a high performance, wide bandwidth oscilloscope with high-speed clock jitter analysis software.
• Maximize the number of measured values (greater than 25,000) for a peak-to-peak measured sigma at or near +/-4.
• Use an oscilloscope sampling rate of 8 GS/Second to capture multiple samples on the leading edge.
• Use a well-designed test fixture with proper clock load to preserve the cleanliness of the signal edges.
• The oscillator under test must use a low noise power source. It is recommended to use a 4.7 uF capacitor in parallel with a 0.01 uF capacitor on the power line next to the oscillator. "

In patricular the 25,000 samples and the 8GS/Second data rate, how to reduce this and still record useful data ?


 


----- Original Message ----
From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
To: Tom Van Baak <tvb at leapsecond.com>; Discussion of precise time and frequency measurement <time-nuts at febo.com>
Sent: Sunday, April 13, 2008 8:42:55 PM
Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider?

Tom
Tom Van Baak wrote:
>> If minimising the PPS jitter, is important adding a single D flipflop to 
>> resynchronise the output PPS signal to the 5MHz input will be worthwhile.
>> A relatively complex chip like a PIC is likely to produce a PPS output 
>> signal with a jitter much greater than that produced by a single flipflop.
>>    
>
> Bruce, double check the PIC data sheet and see if this is really
> true. They are not complex chips; they run DC to 10 MHz, and
> all outputs are synchronous with the clock.
>
>  
The trouble is there is no jitter specification, I was rather hoping 
that someone had actually measured the jitter.

Timing modulation will depend on simultaneous switching effects and the 
occurrence of asynchronous events as well as the impedance of the chips 
internal ground and power wiring as well as bond wire inductances etc.

Some of the more complex PICs have internal PLLs which will inevitably 
increase the internal noise and consequently the output jitter.
The less complex chips may have similar jitter to HCMOS parts although 
its hard to be certain given the poor propagation delay characterisation 
data in the PIC datsheets I have seen.
Your implementation using a PIC without an internal PLL and having a 
fixed instruction execution and periodic sequence should help minimise 
random jitter. <snip>

 


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