[time-nuts] 5 MHZ PIC PPS Divider?

[Bruce Griffiths]

Stanley Reynolds wrote:
>
> ----- Original Message ----
> From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
> To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
> Sent: Tuesday, April 15, 2008 7:54:21 PM
> Subject: Re: [time-nuts] 5 MHZ PIC PPS Divider?
>
> Stanley Reynolds wrote:
>   
>> <snip>
>> "Using a ripple counter is a particularly bad idea, guaranteeing reliable 
>> sampling is likely to be difficult to impossible unless the counter is 
>> capable of reliable operation at several GHz.
>> The problem being the ripple clock propagation delay from one flipflop 
>> to the next. For this counter the input clock to output transition delay 
>> is typically over 4nsec whilst the clock to Q0 delay is about 1.7ns a 
>> difference of 2.3 cycles at 1 GHz.
>>
>> Bruce"
>>  
>> Yes but if the PIC controls the counter Hold control you should have more than enough time for the counter to settle on the order of  > .5sec < 1 sec when measuring a PPS signal. The chip cost is abt 8 USD . I was looking at this device because of it's speed and low cost the ripple delay was just a trade off, just as the low speed interface to the PC and limited data collected is a trade off.
>>
>>
>>  
>>     
> Stanley
>
> You still need a 1GHz synchroniser (ECL dual D flipflop or shift 
> register) for reliable operation when using the synchronous hold input 
> (dont try using the asynchronous hold function as it is much more 
> difficult to get this to work reliably).
>
> Range is only 256 ns so that when testing an oscillator with a 
> relatively large instability or frequency offset count wrapping will be 
> a problem.
>
> Bruce
>  
> I was thinking of using a counter in the PIC for extending the range, could also cut the clock rate if needed, but a 16 bit counter in the PIC if it would work at 38 Mhz.
>  
> I notice that the chip has a number of controls, the asynch start and synch start as well as the low to high transition on the clock input: 
>  
> http://www.onsemi.com/pub_link/Collateral/MC10E137-D.PDF
>  
> Table 2 the sequential truth table list the functions 
>  
> When you say reliable what is the error you mean ? A missed count of 1 out of a 100 should be acceptable.
>  
> Page 7 lists several application notes "AN1504/D − Metastability and the ECLinPS Family"
>  
> http://www.onsemi.com/pub_link/Collateral/AN1504-D.PDF
>  
> I think this is what you are trying to tell me, if so I will study it. 
> Or any reference you could recommend ? 
> On-line references appeal to my cheap nature, and I want it now conditioning.
>
>
> _______________________________________________
>   
Stanley

That application note will give you an introduction to metastability.

A pair of multi GHz D flipflops should ensure that the probability of
metastability is less than once in a hundred years or longer.

Just make sure you wait long enough for both the ECL and the extension
counters to settle.

A better method is to read a very long counter on the fly (64 bits or
more) at the (synchronised) PPS edge. However with ripple counters this
gets tricky as one has to sample each bit at suitable times to ensure
that the sampled count is actually valid.

Software extension of the count chain (after the PIC counter) is also
possible.

I'd just interpolate a 10MHz clock: you can do this all with a PIC and
ADC and some inexpensive analog hardware.

Bruce