[time-nuts] Phase noise & Jitter

[Don Collie jnr]

Hi Ulrich and Bruce,
    OK Ulrich, so one way to combat jitter is to use logic with the fastest possible hi/lo, and lo/hi transitions - slow logic [like CMOS] is more prone to jitter than, say, ECL - have I got that right? Or are you referring to the jitter that arises from noise on an anologue [say : sinewave] signal as it is "squared" into a digital pulse train? I can see how noise on this sinewave would add uncertainty to the time at which the lo/hi, or hi/lo decisionpoint was reached, causing jitter, and hence the importance of having a high SNR analogue signal, when you wish to produce a jitter free digital signal from it. I am more wondering about the jitter produced *in* digital logic itself [particularly frequency synthesisers], even when the reference signal is almost free of it. What are the mechanisms at work in the logic gates that produce this problem, and consequently what steps can be taken to minimise it? If the pulses reaching the phase detector, from the logic part of the circuit, are jitter free, you will have one less thing to worry about when it comes to building a low phase noise PLL, whose output is then put to  good use.
    The other question I had is : What makes a good [ie low
phase noise] PLL ?  Does a high "Q" tuned circuit help, and, if so, why? [the *why* puzzles me] Should you use a low noise active device? [surely this couldn`t hurt] Should the amount of positive feedback used, be only enough to sustain oscillation? Would a levelled [class"A"] oscillator be better than one that limits/saturates?[ie : "class C"] 
    Is it *really* possible to "clean up" jitter, which presumably can have components down to low frequencies, with, say, a PLL? [The assumption being that the loop filter will prevent any phase modulation of the VCO - by filtering out the frequency components present due to jitter]
    I guess the main question here is why does an oscillator
produce noise sidebands at all? [not just a VCO, but any oscillator]
    OK Bruce, I can see how noise on the output signal of a VCO will cause frequency sidebands close to the output frequency of the divider - ie jitter on the divider output.
    It looks as if there is no such thing as a free meal : If you try to get rid of noise on an analogue signal by squaring it into a pulse train, you end up with jitter, whose frequency component is near the PRF[nothing at frequencies down to DC?].
    I`m sorry, but I don`t understand what you mean in your second sentence Bruce.
    Thankyou for your comments, both!....................Don C.