[time-nuts] How do you minimise jitter?

[SAIDJACK at aol.com]

Hello Don,
 
close-in phase noise within the PLL loop filter bandwidth in Synthesized  
Signal Generators is a quality of the components used (among others), and  the 
optimization of the design.
 
For an output that is generated directly by the Oscillator (not a  divider 
chain, DDS etc) three main noise sources are present:
 
Within the loop bandwidth of the PLL:
 
1) the phase noise of the reference (for example DDS output, crystal  
oscillator output, etc).  The output generally cannot be better than  
20log(Fout/Fref)+NoiseFloorFref for example.
 
2) The PLL chip used. For example the same circuitry using an ADF4153 (ADI)  
PLL versus an LMX2316 (N.S) has in our products generated much  less close-in 
phase noise with the ADI chip (more than 10dB difference),  all else being 
identical. Both chips are footprint compatible.
 
For frequencies outside the loop bandwidth:
 
3) noise of the oscillator
 
For example, high-end synthesizers will use wideband YIG oscillators with  
extremely low phase noise. This allows the loop bandwidth to be much smaller  
than using a VCO, so their noise level is significantly less than VCO based  
products.
 
One drawback: prices of YIGS can be $500, $1000, or even much more for this  
reason, and for their greater than octave performance and level stability etc. 
A  typical VCO will cost only <$50.
 
bye,
Said
 
 
In a message dated 4/27/2008 21:32:24 Pacific Daylight Time,  
df6jb at ulrich-bangert.de writes:

>  I`ve been puzzling over the reasons why one synthesised 
> signal  generator produces more close-in noise than another,  





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