[time-nuts] DMTD mixer question

pablo alvarez pabloalvarezsanchez at gmail.com
Fri Dec 5 11:57:09 UTC 2008


Hi,

Perhaps the most apropiate solution for the time-nuts world is to use
an standard development kit and add a custom mezzanine with the extra
required logic.

Unfortunately the one I have in my lab is based on a Virtex5 fpga
which is rather expensive, but one can find excelent solutions for
200$
For example:
http://www.xilinx.com/products/devkits/HW-SPAR3AN-SK-UNI-G.htm

The mezaninne card would contain SMA connectors,  an array of ECL
registers and the PLL that should generate the reference frequency.

In the FPGA we will just do the PLL control, counting and external
world interface (probably the simplest is to go for the good old
rs232).
In principle I will do all the code in VHDL so you will not have any
problem in porting it to any device.

Cheers

pablo


On Thu, Dec 4, 2008 at 2:18 AM, Bruce Griffiths
<bruce.griffiths at xtra.co.nz> wrote:
> pablo alvarez wrote:
>> thanks for the positive feedback,
>>
>> In xilinx fpgas, for example, the recovery time after a metastability
>> issue is quite fast as reported in this paper
>>
>> http://www.xilinx.com/support/documentation/application_notes/xapp094.pdf
>>
>> The capture window of metastable state is 0.01fm (page 2). Probably
>> this window is moving around a bit, but this 0.01fm sounds promising.
>>
>> In page 3 "When granted 2 ns of extra settling delay, the problems
>> caused by metastability are almost eliminated, as their MTBF exceeds
>> millions of years."
>>
>> So we can just solve the glitch problem by adding a shift register as
>> Bruce suggested.  I think the major concern may be crosstalk, but
>> using lvds or ecl logic and placing the IOs far away one from each
>> other may help to reduce it a bit.
>>
>>
>> Now a DMTD architecture can be almost completely based on a FPGA where
>> some LVDS  IOs would contain the D flip-flop mixers, with their clock
>> input connected to the reference frequency and the D input to the
>> clocks under test. The FPGA would contain a 32 bit free running
>> counter clocked by the reference clock. Every time I detect a
>> transition on my LVDS IOs the free running counter is latched and
>> passed to a FIFO. Then the work can be passed to a data analysis
>> program (of course through an LVDS serial link)  to do all sort of
>> funny calculations.
>>
>> I wonder how good this system could eventually be if we reduce
>> crosstalk to a minimum.
>>
>>
>> Pablo
>>
>>
>>
>> On Wed, Dec 3, 2008 at 9:01 PM, Bruce Griffiths
>> <bruce.griffiths at xtra.co.nz> wrote:
>>
>>> Lux, James P wrote:
>>>
>>>>>> Cheers
>>>>>>
>>>>>> Pablo
>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>> Pablo
>>>>>
>>>>> Flipflop mixers tend to produce glitches at the beat
>>>>> frequency transitions.
>>>>> A digital PFD in a PLL doesnt produce a beat frequency output
>>>>> when locked so such glitches arent a problem,
>>>>>
>>>>>
>>>>>
>>>> I don't know that this is the case with modern PLL PFDs.. If only because glitches at the transitions would cause other problems, so there's an incentive to get rid of them.
>>>>
>>>>
>>>> Jim
>>>>
>>>>
>>>>
>>> Surely metastability may occur when the mixer flipflop D input
>>> transitions occur close to its active clock transitions?
>>>
>>> There is at least one patent (US5053651) that claims to eliminate such
>>> glitches in a digital mixer, however its output beat frequency is half
>>> the difference between the input frequencies.
>>>
>>> Bruce
>>>
>>>
> Pablo
>
> A DMTD system implemented largely in an FPGA should reduce cost
> considerably and perhaps place such systems within the reach of more
> time nuts.
>
> One can also exploit process variations by using several such systems in
> parallel to produce even more information in the vicinity of a
> coincidence between active clock and D input transitions.
> However crosstalk may be even more problematic in this case. despite
> potential crosstalk problems arrays of arbiters driven in parallel have
> successfully exploited statistical process variations to increase the
> effective resolution.
>
> Bruce
>
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