[time-nuts] Sub Pico Second Phase logger

[Bruce Griffiths]

Joe

Joe Gwinn wrote:
> Bruce,
>
> At 3:54 AM +0000 12/19/08, time-nuts-request at febo.com wrote:
>   
>> Message: 5
>> Date: Fri, 19 Dec 2008 16:51:55 +1300
>> From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>> Subject: Re: [time-nuts] Sub Pico Second Phase logger
>> To: Discussion of precise time and frequency measurement
>> 	<time-nuts at febo.com>
>>
>> Joe
>>
>> Joe Gwinn wrote:
>>     
>>>  At 11:48 PM +0000 12/18/08, time-nuts-request at febo.com wrote:
>>>  
>>>       
>>>>  Message: 5
>>>>  Date: Fri, 19 Dec 2008 12:48:27 +1300
>>>>  From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>>>>  Subject: Re: [time-nuts] Sub Pico Second Phase logger
>>>>  To: Discussion of precise time and frequency measurement
>>>>         
>>  >>	<time-nuts at febo.com>
>>  >>
>>  >> [snip]
>>  >  
>>     
>>>>  Using a second sound card to generate the test signal may overcome this
>>>>  problem at increased cost, and for some it may not even be an option.
>>>>         
>>  >>    
>>     
>>>  It may not work with PCI soundcards, as the card clock may be
>>>  synchronized to the PCI bus clock.  Firewire/USB cards will have
>>>  their own independent clocks.
>>>
>>>  
>>>       
>> Most recent design PCI sound cards have their own independent crystal
>> oscillator.
>>     
>
> It won't be a great crystal, but a crystal nonetheless.
>
>   
The AP192 has 2 low profile HC49 style crystal packages on the PCB.
>   
>> Some claim to be able to sync to an SPDIF input but the resultant jitter
>> may be large.
>>     
>
> Why large jitter?  Bad implementation?
>
>
>   
I'm just suspicious, although I did see some data somewhere that seemed
to confirm my suspicions.
The S/PDIF signal has to be a valid SPDIF signal not just a square or
sine wave clock.
Output sample rates (for the AP192) are then identical to that of the
the S/PDIF source which is limited to
192, 176.4, 96,88.2 48, 44.1 32 KSPS.
>>  >  
>>     
>>>>   >> 10Hz resolution whilst avoiding phase truncation spurs is impractical
>>>>    
>>>>         
>>>>>>   with a DDS chip by itself.
>>>>>>   Depending on the DDS and its clock frequency, the frequency spacing of
>>>>>>   phase truncation spur free outputs may be as large as several kHz.
>>>>>>   
>>>>>>
>>>>>>             
>>  >>>  Is this true of concatenated DDS chips?  I recall a patent to the
>>  >>> contrary.
>>  >>  >
>>  >> Which patent?
>>  >
>>     
>>>  Hmm.  It's at work.  I'll look it up in January.  As I recall, the
>>>  second DDS made a small integer conversion, and so had low spurs,
>>>  while the first DDS was set to whatever was needed.
>>>
>>>
>>>       
>> Do you mean US5598440?
>>     
>
> Yes, that's it.
>
>
>   
>>  >> If the zero crossings are time stamped and do not occur simultaneously
>>     
>>>>  in each channel then the phase noise of the offset oscillator will
>>>>         
>>  >> affect the measurement.
>>  >
>>     
>>>  I'm not following.  Please expand.  The zero crossings are never
>>>  aligned unless there is no phase delay.
>>>
>>>
>>>  
>>>       
>> Yes, thats the point, the offset generator phase noise contribution isnt
>> the same for both zero crossings.
>> Greenhall et al correct for this to some extent, but at least for short
>> tau, one is then no longer measuring ADEV, MDEV etc.
>> There is some advantage in having a higher beat frequency as the offset
>> generator phase noise has less time to accumulate.
>>     
>
> I recall reading an article on this by Greenhall, probably _the_ 
> article.  My reaction was that I would be fortunate to have a setup 
> where I could even detect such a problem.
>
>
>   
>>  >>  >> A few divide and mix stages will be required to achieve a spur free
>>     
>>>>    
>>>>         
>>>>>>   resolution of 10Hz.
>>>>>>   
>>>>>>        
>>>>>>             
>>>>>   That is a traditional approach.  But are there alternate approaches that
>>>>>   have now become practical?
>>>>>
>>>>>
>>>>>      
>>>>>           
>>>>  Diophantine frequency synthesis?
>>>>    
>>>>         
>>>   From the sound of the name I think so, at least in the last DDS
>>>  stage, as done by that patent.
>>>
>>>  But I was fishing.
>>>
>>>  
>>>       
>> Conventional Diophantine synthesis uses number theory together with 2 or
>> 3 conventional synthesiser loops to achieve very fine resolution whilst
>> maintaining a high PLL phase detector input frequency.
>>     
>
> In a sense, the concatenated DDS approach is a divide-and-mix chain. 
> Perhaps there is a parallel here.
>
>
>   
The DDS based equivalent (of the dual PLL Diophantine synthesiser) would
use a pair of DDS chips each replacing a conventional PPL in the
Diophantine frequency synthesiser, the output frequency of each having
zero phase truncation spurs.
Both DDS clock sources should be spur free and have a frequency ratio
that is a selected fixed rational fraction.
A conventional mixer would then be used to either add or subtract the
two DDS output frequencies.
If the ratio of the 2 DDS clock source frequencies is appropriately
chosen the spacing between the resultant mixer output frequencies can be
much finer than the spacing between the truncation spur free outputs of
either DDS chip.
The DDS and mixer outputs should be filtered to remove harmonics and
other unwanted frequencies.

One drawback is that selecting the output frequencies of the 2 DDS chips
required to produce the desired output frequency is somewhat complex.
Since one almost certainly needs a computer of some sort to set the DDS
frequencies this shouldn't be a significant issue.

Bruce