[time-nuts] Sub Pico Second Phase logger
Bruce Griffiths
bruce.griffiths at xtra.co.nz
Tue Dec 23 19:47:21 UTC 2008
Joe
Joe Gwinn wrote:
> Bruce,
>
> At 11:43 PM +0000 12/22/08, time-nuts-request at febo.com wrote:
>
>> Date: Tue, 23 Dec 2008 12:01:40 +1300
>> From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>> Subject: Re: [time-nuts] Sub Pico Second Phase logger
>> To: Discussion of precise time and frequency measurement
>> <time-nuts at febo.com>
>>
>> [snip]
>> >> [BG] Control of the close in spur levels produced by the NCO
>> may also be an
>>
>>>> issue.
>>>>
>>>>
>>> [JG] If the division ratio is an integer, the spurs are reduced.
>>>
>>> Analog Devices has a web calculator that's useful for fast
>>> exploration. The calculator operation is explained and the reference
>>> provided in their big tutorial on DDS principles.
>>>
>>>
>>>
>>>
>> It's a bit misleading in that it indicates that the performance is
>> impaired when there is no phase truncation spur.
>>
>
> I just look at the spur chart.
>
>
>
>> This may well be true for frequencies close to that frequency that has
>> no phase truncation spur, however in this application one wouldn't
>> choose an output frequency that has significant phase truncation spurs.
>>
>
> The value of the calculator is to look around for such sweet spots.
>
> One can also generate the traditional spur chart, the one with the
> nest of diagonal lines.
>
>
>
>> >>> I found and read the basic articles, which can be downloaded from
>>
>>>>>
>>>>>
>>>> > Prof Sotiriadis' website:
>>>>
>>>>
>>>>> <http://www.ece.jhu.edu/~pps/WEB/Publications/pub.html>
>>>>>
>>>>>
>>>>>
>>>>>
>>>> [BG] There is also US patent 5267182.
>>>>
>>>>
>> > I did find 5,267,182 while searching for Sotiriadis' patent, but
>>
>>> forgot to mention it. Don't know what the difference is. In the US,
>>> patent applications are made public after 18 months, or immediately
>>> if the person is also applying for a European patent. The US Patent
>>>
>> > Office is years behind, so patent issuance may be a while.
>>
>
> I just read 5,267,182. It appears to anticipate Sotiriadis in every
> aspect, so it may be a *long* time before Sotiriadis's patent is
> issued.
>
>
>
>> >> > Items J10, J13, and J15 seem particularly relevant.
>>
>>>> >
>>>>
>>>>
>>>>> All one needs is the M/N chip, although one can certainly use DDS chips.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>> Using a DDS avoids the requirement for a pair of low phase noise VCOs.
>>>>
>>>>
>>> If we can control the spurs, many DDS chips are very good.
>>>
>>>
>>>
>> A DDS, unlike a conventional digital frequency divider, doesn't suffer
>>
> >from aliasing of phase noise into the output passband.
>
> How true is this, in practice? A DDS is at the mercy of phase noise
> in its reference clock, by much the same mechanism as for a simple
> divider chain. And the variable-factor dividers (the M and N above)
> work in a manner similar to a DDS, but with far coarser increments
> and limits. Both DDS and M/N PLL chips use a PLL to clean up the
> resulting ref signal. Many DDS chips incorporate a M/N PLL to
> multiply the ref frequency.
>
>
>
For NIST's measurements of this effect see:
http://tf.nist.gov/timefreq/general/pdf/1380.pdf
>> >> >> >> A conventional mixer would then be used to either add or
>> subtract the
>>
>>>>
>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>>>> two DDS output frequencies.
>>>>>>>> If the ratio of the 2 DDS clock source frequencies is appropriately
>>>>>>>> chosen the spacing between the resultant mixer output
>>>>>>>> frequencies can be
>>>>>>>> much finer than the spacing between the truncation spur
>>>>>>>> free outputs of
>>>>>>>> either DDS chip.
>>>>>>>> The DDS and mixer outputs should be filtered to remove harmonics and
>>>>>>>> other unwanted frequencies.
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>> If the DDS chips are well chosen, we will get sin and cos outputs,
>>>>>>> and so can implement a dual-mixer phasing scheme to yield only the
>>>>>>>
>> >>>>> sum frequency or only the difference frequency, greatly reducing the
>>
>>>>>>> amount of filtering needed. The better balanced the channels are the
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>> > better the cancellation of the unwanted term. This is basically the
>>>>>> > phasing method of single-sideband signal generation.
>>>>>>
>>>>>>
>>>>>>
>>>>> This would be a reason to use DDS chips instead of M/N PLL chips,
>>>>> unless there are M/N PLL chips that provide quadrature outputs.
>>>>>
>> >>> SiLabs Si5338 may suffice, as it allows one to control the relative
>>
>>>>> phase of its outputs.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>> If one were to divide the output frequency of the diophantine
>>>> synthesizer by 4 using a 2 bit Johnson counter then quadrature phase
>>>> outputs are available.
>>>> However the filters used to extract the fundamental from the divider
>>>> outputs would need to be matched.
>>>> If the diophantine frequency synthesiser output frequency doesn't vary
>>>> too much one can always use a quadrature hybrid.
>>>>
>>>>
>>> This seems like a lot of work. Hmm. Now that I think of it, the
>>> SiLabs chips emit square waves (logic signals), not sine waves. Back
>>> to DDS chips, it seems.
>>>
>>> Joe
>>>
>>>
>>>
>> The simplest way of achieving the required performance is preferable.
>>
>
> Yes, but aren't we Time Nuts?
>
>
Usually with finite budgets.
> Joe
>
>
Bruce
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