[time-nuts] GPS Locked and Unlocked Performance Comparison

[Bruce Griffiths]

SAIDJACK at aol.com wrote:
> Hello Tom,
>  
> Bruce mentioned there is a validity bit that can be checked for holdover. I  
> wonder if a small micro can be used to hold the EFC voltage steady without 
> much  effort. Or maybe using Super-Caps in the loop filter?
>  
> Or maybe use one of those new 24 bit Sigma-Delta ADC/DAC chips to capture a  
> 24 bit word (ADC) and feed that to the 24 bit DAC during holdover. Kind of a 
> 24  bit high-precision sample-and-hold circuit.
>  
> It would be a shame to have such a good OCXO performance go unused during  
> short hold-overs. Interesting technical challenge.
>  
> bye,
> Said
>   
Said

If the analog filter is an active PI filter then a low leakage analog
switch in series with the input resistor will work for short hold times,
for extended hold times a digital sample and hold of some sort will be
necessary. Since it is likely that the input to the EFC has been
attenuated to reduce the PLL natural frequency without requiring
impractically long analog filter time constants, a 16 bit DAC may well
suffice. A heavily overdamped PLL loop would explain the poor tracking
of the OCXO characteristics at relatively small Tau.

One could easily implement a classical tracking ADC (DAC + comparator)
so that the DAC output tracks the PLL filter output to within 1 LSB
during normal operation.
An analog switch can then be used to switch tfrom the PLL filter output
to the DAC output during holdover.
It would also be necessary to use an analog switch in series with the PI
filter input resistor and for extended holdover keep the PI filter
feedback cap charged at the DAC voltage to minimise transients on
reverting to normal operation.

Bruce