[time-nuts] Low phase noise digital divider (in 600MHz to10MHz area)
Grant Hodgson
grant at ghengineering.co.uk
Fri Jan 25 18:08:39 UTC 2008
Anders
One option is to use just the programmable divider part of a PLL IC,
such as those from National Semiconductors or Analog Devices. Or, use a
Hittite HMC394 programmable counter preceded by a fast /2 flip flop.
The PLLs will need serial programming via a micro-controller or other
logic device; the HMC394 uses parallel programming so is easier to
implement.
Neither the PLLs nor the HMC394 counter need external edge conditioning
- they will work with sine wave inputs.
These solutions won't give you as good a phase noise performance as a
regenerative divider, but if you want something that you can just plug
together then they will work for relatively little effort. And you
don't need to worry about -ve supply voltages which some ECL devices need.
regards
Grant
> From: "Anders Time" <anderstime at gmail.com>
> Subject: [time-nuts] Low phase noise digital divider (in 600MHz
> to10MHz area)
> To: time-nuts at febo.com
> Message-ID:
> <7a60526d0801250501u78df61bbm419520baec84762 at mail.gmail.com>
> Content-Type: text/plain; charset=ISO-8859-1
>
> Have been locking around for a good article on how to design a good Low
> phase noise digital divider(in 600MHz to 10MHz area), but the have not found
> any good literature. Today most people talk about regenerative dividers, but
> are a rather complex subject.
> Does anyone have experience in what logic family that have the lowest noise
> TTL, AC, HC, F etc?
> What is the upper limit for ECL diviers? My first idea was to use ECL to
> divide down to 100MHz area and then to use lower noise TTL to go down to
> 10MHz.
> What about edge-conditioning circuit at divider input? Have seen people talk
> about it, but no info what it does?
> Thanks
> Anders
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