[time-nuts] Low phase noise digital divider (in 600MHz to10MHzarea)

[John Miles]

> One option is to use just the programmable divider part of a PLL IC,
> such as those from National Semiconductors or Analog Devices.  Or, use a
> Hittite HMC394 programmable counter preceded by a fast /2 flip flop.
> The PLLs will need serial programming via a micro-controller or other
> logic device; the HMC394 uses parallel programming so is easier to
> implement.
>
> Neither the PLLs nor the HMC394 counter need external edge conditioning
> - they will work with sine wave inputs.

... at high input frequencies.  The Hittite parts *hate* sine-wave inputs
below about 100 MHz.  Sensitivity drops like a rock (and presumably jitter
performance does too, but I haven't looked closely at that).

The NatSemi/ADF PLL chips are fine with whatever you give them,
sensitivity-wise, although they are quieter if you don't rely on them to do
their own edge conditioning.

> These solutions won't give you as good a phase noise performance as a
> regenerative divider, but if you want something that you can just plug
> together then they will work for relatively little effort.  And you
> don't need to worry about -ve supply voltages which some ECL devices need.

The Zarlink SP8401 and SP8402 are also worth investigating.  They are the
quietest VHF/UHF divider chips I'm aware of.
http://products.zarlink.com/product_profiles/SP8402.htm

-- john, KE5FX