[time-nuts] Frequency divider design critique request

[Bruce Griffiths]

Magnus Danielson wrote:
> I would consider a dedicated 1 PPS output.
>
> I would consider a synchronise feature with a PPS/synchronise input. It should
> be wise to not directly wire it to the counter resets, but provide an arm
> button and maybe a very simple arrangement to indicate "left", "on mark" and
> "right" with red, gren, red LEDs. Just a tought. The arm button could also
> have an electrical input, but I am running into creaping featurism here.
> I think however that synchronisation might be a good thing. That way you can
> shift the phase of the signal to fit your need. Pulling and inserting the
> 10 MHz cable is a very crude way of doing it.
> Maybe it would be just too much fuzz for too little gain, what do I know, but
> I know I would enjoy seeing it.
> A pulse-add/pulse-swallow technique (with a shift in initial divide by 10)
> could be used to provide inc/dec functionality for a manual movement of phase.
>
> Cheers,
> Magnus
>
>   
Hej Magnus

The easiest way to add a synchronise feature is to use a shift register 
clocked at 10MHz (if the input PPS pulse width is sufficient > 1us?) as 
the synchroniser.
The various shift register taps can be used to generate a synchronous 
preload pulse for the input divider and a wider reset pulse for the 
74HC4017's.

If narrower sync pulses are likely then use the sync pulse to toggle a 
flipflop than connect the flipflop output to the shift register input 
and use 74XX86 XOR gates to generate the preload and REST pulses from 
the shift register taps.

Bruce