[time-nuts] Frequency divider design critique request

[time at johnea.net]

On Fri, Jul 11, 2008 at 11:33:53AM +1200, Bruce Griffiths wrote:
> time at johnea.net wrote:
> > Hi David,
> >
> > It looks like your design is pretty far along, so maybe it's too late for this suggestion, but one thing you might consider is replacing the 7400 series logic with a 5V CPLD programmable logic device.
> >
> > This could offer several advantages:
> >
> > 1) any issues (such as jitter) could be addressed by reflashing the CPLD and may let you avoid hardware PCB changes.
> >   
> You cannot "fix" modulation of the higher frequency divider outputs by 
> lower frequency outputs by reprogramming a CPLD or FPGA.
> External reclocking/resynchronising flipflops (one per output frequency) 
> are required

Flip flops within the CPLD can be clocked with completely asynchronous clocks and perform the exact function of devices external to the CPLD.

> >
> > The ISE design tool offers built in Verilog, VHDL or CUPL programming laguages, or (and this really amazed me) a built in schematic editor tool! This lets you capture the design, just as you have, in a schematic, and then synthesize the logic and perform a complete simulation of your captured schematic.
> >
> > You could even just download the tool, capture your existing schematic (there are logic elements for 7400 series logic devices) and use the tool as a simulation engine to test your design. Even if you ultimately plan to use the 7400 parts.
> >
> >   
> Just dont use this method to implement the dividers etc in the CPLD.
> Its better to use a fully synchronous decade divider chain if possible 
> as this eliminates all the realignment logic required with ripple 
> clocked divider chains.
> 

Excellent point. While you could capture your existing design in it's exact form for simulation purposes, if you intended to use the CPLD as the final target device, a fully synchronous divider would be best. The symbol libraries contain a very nice full look ahead counter which is cascadable to arbitrary width.

In fact Bruce's point of using synchronous design practices really applies equally to designs within a CPLD/FPGA or implimented using discrete components.

> Another issue with some (but not all) CPLDs are the power supply 
> requirements, at least with CMOS the divider (when not driving too many 
> outputs) has a low power supply current making battery operation feasible.

I would expect that replacing the many 74HCxx logic devices with one CPLD would provide a power consumption benefit. 

BTW, Altera also offers a very full featured design tool for their programmable logic devices viia free download, but I haven't tried it as it's available for windows only.

johnea