[time-nuts] Test equipment-level phase noise PLLs

[John Miles]

I've played with the Hittite chips before and obtained PN results in the
same ballpark (see http://www.ke5fx.com/hpll.htm ), but at 8 GHz rather than
6 GHz.  To save further head-scratching, the figure of merit on these chips
works like this:

In-band phase noise in dBc/Hz = FOM + 10*log(Fcomp) + 20*log(N)

This is the best-case noise level that you will get assuming a
perfectly-clean reference and no VCO noise contribution.  As usual,
Hittite's less-than-ideal data sheet doesn't make that relationship clear.

Specifically, the 5.8-GHz integer-N plot in figure 1 appear to have been
made with a 50 MHz comparison frequency and N=116.  -107 dBc/Hz - 77 - 41
= -225 dBc/Hz.

>From that relationship, you can see that minimizing N is the most important
thing you can do.  Good-quality signal generators work on the basis of
minimizing N at all costs.  Fractional techniques are common but the
ultimate performance still comes from cascaded or nested synthesis stages
with an integer-N output loop.

The HP 8672/8673 family, for instance, uses a comparison frequency (really a
harmonic sampler drive signal) in the 200 MHz neighborhood.  They still
don't achieve inband PN better than about -100 dBc/Hz, because the earlier
stages that generate the Fcomp signal are relatively noisy.  It's safe to
say that your R&S synthesizer uses a similarly-low N factor, cleaner
reference synthesizers, and a cleaner output loop.

The easy way to get a few more dB out of the Hittite chip would be to run
with an Fcomp in the 100 MHz vicinity instead of 50 MHz.  It is rated for
Fcomp <= 140 MHz in the (quieter) integer-N mode.

-- john, KE5FX


> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com]On
> Behalf Of Matt Ettus
> Sent: Tuesday, July 22, 2008 1:16 PM
> To: Discussion of precise time and frequency measurement
> Subject: [time-nuts] Test equipment-level phase noise PLLs
>
>
> In looking into extremely low phase noise synthesizers, I have come
> across the new HMC700LP4 chip from hittite, which seems to have the
> best figure of merit I have found, -227 dBm/Hz.  That gives you
> -107dBc/Hz at 20 kHz offset at 6 GHz according to the datasheets.
>
> That sounds amazingly good, but my R+S signal generator does better.
> Do they use a different sort of architecture?  Do they not use
> conventional dividers?  Some other sort of phase detector?
>
> Thanks,
> Matt
>