[time-nuts] 32768Hz from 10MHz
richard at karlquist.com
Wed Jul 23 15:08:37 EDT 2008
These limitations only apply because you have chosen an
accumulator size that is a binary power (ie 2^N). If
the accumulator is modulo 78,125 (ie 5^7), and you load
the value 256 (ie 2^8) every 100 nsec, the accumulator will overflow
at the rate of 32768 Hz, on the average. And it will be
exact, on the average. There is an easy way to implement this.
Make the accumulator, say, 131,072 (ie 2^17). Each time it
overflows, add an extra 52,947 to it (ie 131,072 - 78125).
This will make it look like it has the size of 78,125. I'm
sure you can figure this out. You can still use a binary word
size for the DAC data.
Rick Karlquist N6RK
Murray Greenman wrote:
> There is no easy way to divide directly from 10MHz to 32768Hz.
> On my web site at www.qsl.net/zl1bpu/MICRO there are several signal
> generator projects which would do the job of generating 32768Hz from
> 10MHz for you.
> With any of these (single chip micro approach, using 24-bit Direct
> Digital Synthesis) the closest you'd get would be to load 078CBC into
> the DDS. The result would be 32767.9846Hz, an error of 0.47ppm (14
> By extending the algorithm to 32 bit, as I did in my LF Exciter, the
> step resolution improves to 0.23mHz, and by loading 8637BD0 you'd
> generate 32767.999917 Hz, or an error of 2.5ppb. To put it into
> perspective, that's an error of 8 seconds in 100 years!
> Similar maths would apply to any micro-based DDS. I suggest adapting my
> design purely because it's simple, and a chip like the ATTiny2313 is
> well suited to the job.
> Murray ZL1BPU
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