[time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Thu Jul 31 04:58:16 EDT 2008

SAIDJACK at aol.com wrote:
> Hi Bruce,
> that would work too. We get <330fs jitter rms with this circuit using  the 
> Fairchild UHS LVC family, that's pretty much the noise floor of the  OCXO :)
> If you use a bias network, you won't get 50% symmetry since it will never  
> perfectly match the inverter's inflection point (which changes with temp etc),  
> and you may insert noise from the power supply. With the feedback resistor it  
> will operation at the inversion point without adding power  supply noise.
> bye,
> Said
Yes, however it is quieter and adding duty cycle stabilisation feedback 
fixes that problem.

For even lower noise, bandpass filter the OCXO output (a crystal filter 
is particularly effective).
Its not too difficult to drop the noise floor to a few tens of femtosec.
The drawbacks being the cost, and the need to regulate the bandpass 
filter temperature to minimise phase shift variations with ambient 
You would also need to use a quieter clock driver.
It may even be necessary to use a well designed bandpass limiter to 
increase the signal zero crossing slew rate before using a 6GHz 
bandwidth clock driver.

However the cost and complexity probably isnt justified when driving an 
FPGA which may have tens of picoseconds of jitter.


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