[time-nuts] What is a Time-Nut grade Zero Crossing Circuit?

[John Miles]

>
> I do agree with Richard, comparators are quite bad...
>
> Having played with interfacing signals to FPGA 'ad nausea'
> I found that the only simple scheme that works
> better than biased (or feedback) cmos gates and of
> course much better than ECL line receivers or comparators
> (even cmos gates biased sometimes exhibit some strange issues
> specially when no signal is present)...

Modern ECL parts aren't necessarily that bad compared to the old MECL stuff.
For some reason, though, the one circuit I measured (MC100EL16 line
receiver, driven single-ended) was much quieter at 100 MHz (-150 dBc/Hz
floor) than at 10 MHz (-140 dBc/Hz floor).  I  need to look into that a bit
further.

Point being, benchmarks taken at the usual 10 MHz may not be helpful if you
are actually going to work at higher frequencies.  If the additive jitter
remains constant, the additive phase noise should get worse at higher
carrier frequencies, not better... but that doesn't always seem to be what
happens.

-- john, KE5FX