[time-nuts] Fine delay generator

[Bruce Griffiths]

> Pablo
>
> Surely it would be better to sampled the low pass filtered latched
> trigger transition with a pipeline ADC clocked at 100MHz or more.
> The threshold crossing time of the ADC input can then be calculated from
> the ADC samples (using WSK interpolation etc) provided there are
> sufficient samples taken during the transition.
> The low pass filter delay will have to be taken into account in
> determining the actual time of occurrence of the trigger input signal.
> A long tailed pair with a differential output could be used to drive a
> differential low pass filter connected to the differential ADC input.
> A resolution of 10ps or better should be achievable with the offset
> stability largely determined by the analog filter delay instability (due
> to time, temperature etc).
> The slope should be very stable as it is largely determined by the ADC
> clock and ADC linearity.
>
> Bruce
>   

I meant to say that using a higher resolution pipeline ADC than the
AD9626 may be better as the SNR limits the AD9626 to about 10.5 bits at
low input frequencies.
This means that the equivalent timing noise will be around 14ps if the
ADC input has a 10ns transition time and the ADC is clocked at 250MHz.
An ADC with 14 effective bit performance with a 100MHz sampling clock
should have an equivalent timing noise of around 5ps or so when the ADC
input has a 25nS transition time.
An AD9446 should achieve a timing noise level of around 7ps rms or so
when clocked at 100MHz.

A pulse centroid timing technique using an ADC to sample a quasi
Gaussian pulse has been demonstrated to have a stability of 10-20ps or
so after calibration.
A timing technique using WSK interpolation should have somewhat greater
stability as the analog signal processing required is much simpler.

Bruce