[time-nuts] [Fwd: Re: What is the best counter for a Time Nuts?]
Steve Rooke
sar10538 at gmail.com
Fri Oct 17 18:30:14 UTC 2008
2008/10/17 Mike Monett <XDE-L2G3 at myamail.com>:
> Those are all variations of an XOR. This is perhaps the worst
> possible phase detector to use for precision applications. It has
> very high ripple at lock, which generates unwanted sidebands in the
> PLL oscillator output.
>
> It requires signals 90 degrees out of phase, so you have to add
> extra logic to lock to signals that are in phase. This adds jitter.
>
> The output is not referenced to ground, but to some floating level.
> This means very small offsets and drift will change the lock point.
>
> It is also unsuitable for measuring phase angle. The slope of the
> transfer curve for the basic XOR reverses at +/- 90 degrees. So you
> can't use it to measure phase angle.
>
> The AD9901 hase all the above problems but it rails at +/- 180
> degrees instead. It cannot be used to measure phase angle either.
>
> The standard phase/frequency detector (PFD) is better for precision
> PLL's since the output signal is zero at lock. This means minimum
> ripple to generate sidebands. It can be reset to a known state so it
> can be started in phase with an incoming signal. This greatly
> reduces the lock time.
>
> It wraps at 360 degrees, so it is also better suited for measuring
> phase angle.
>
> These are only some of the issues in analyzing a phase detector for
> a precision pll. Here is a quickie LTspice analysis showing the
> phase detector transfer curves for the three detectors. I posted it
> so people would not get their mailbox clogged with attachments.
>
> http://silversol.net63.net/spice/phasedet/phasedet.htm
>
> [...]
>
> > The quickest and easiest is to use the AD9901 phase detector as it
> > only has a few ns of non linearity at the end of the range. For
> > higher resolution just add a sigma delta ADC.
>
> The AD9901 is a very bad design. Probably the poorest I have ever
> seen. It is unsuitable for measuring phase angle. Adding a high
> resolution ADC will do nothing to help.
>
> I notice there is very little in the way of analysis on your site.
> This means it is impossible to distinguish one circuit from another.
>
> What you really need to do is go through and put everything in
> LTspice so people can look at the circuit behavior in detail.
>
> Then you need to do a tolerance and sensitivity analysis to show how
> stable the circuits are over long periods.
>
> Then you need to do a noise analysis to show why some circuits are
> better than others.
>
> This would make your information much more valuable and interesting.
>
> One of my big problems right now is trying to understand why the XOR
> works so well in one of the GPSDO's in Tom's Allan variance pages. I
> can't find it at the moment, but I need to take a very close look at
> this design and see what is going on.
One of the greatest problems in any pll circuit is instability caused
by time delays in the feedback low pass circuit. In a locked system
where the feedback voltage approaches the rails, stability improves
due to the lower error signal. Getting the time constant of a simple
low pass feedback circuit right is not easy especially in high
precision phase locked systems. Ideally the filter should have a very
low frequency cutoff but have very low time delay and the two are
usually at odds with each other in simple designs.
73
Steve
--
Steve Rooke - ZL3TUV & G8KVD
Omnium finis imminet
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