[time-nuts] Thunderbolt Monitor (Didier Juges)

[Bruce Griffiths]

Bill

WB6BNQ wrote:
> Hi Bruce,
>
> Well I think you missed my point !  As I mentioned there are a few who have the
> ability to deal with the H and Cs devices.
>
> However, I was really targeting the low end of the spectrum.  I referred to them
> as the "normal guy" but perhaps I should have said the "casual guy" meaning those
> who have a passing interest but are not going to run out and buy a Cs or even a
> Rb but would be happy with a GPS disciplined crystal with 3 to 4 times the
> accuracy they really need.  This person may have a less than stellar counter or
> two laying around who would want to calibrate them against his GPSDO every now
> and then.  Or may want to monitor and calibrate their HF rig for a ARRL frequency
> contest or some such.  Even those with a Rb may not need more then what i
> suggested.
>
> I think the Shera controller with some upgrades is probably more then good enough
> for the targeted level to discipline a crystal house standard or two.  Not that I
> am saying something else could not be used.  Particularly for the third channel
> which would be intended for non disciplined purposes.  I should have made
> reference to the TRACOR 895 for that third position.
>   
A single flipflop plus a micro or 2 (1 if one uses an actual physical 
DAC instead of a software implementation of a high resolution sigma 
delta DAC) is all you really need to achieve close to the best 
performance possible from whatever timing receiver and OCXO that are 
selected. The flipflop resolution automatically adjusts to suit the 
system noise level.

A 74AC74 plus a 74C86 or equivalent in a DIP package together with an 
opamp or 2 plus a high resolution ADC can be used to make a high 
resolution phase comparator if one must use DIP packages. However an 
AD9901 (20 pin PLCC) in a through hole socket is perhaps more convenient 
given that it has all the required logic and signal conditioning to 
implement a phase comparator all it lacks is an opamp or 2 plus a high 
resolution ADC.

Analog Devices do have some high resolution (24 bit) sigma delta ADCs 
available in DIP packages.
> I was also thinking at the kit level.  If things were done at the "thru-hole"
> level maybe more people would be interested in building such a kit.  Usually the
> people left these days that tinker around (i.e., quasi hobbyist) are older with
> failing eye sight, a little more jitter in their step (if you know what I mean)
> and not interested in fooling around with those damn surface mount items {such as
> myself}.  Sticking to "thru-hole" means those putting the kit together do not
> have to figure out how to handle the surface mount stuff for those who do not or
> cannot deal with it.
>
>   
The Digilent CPLD's on DIP compatible daughter cards make it practical 
to implement circuits of intermediate complexity whilst remaining 
through hole component compatible.
Simple stuff like programmable dividers that don't require a large 
number of ZdIP packages, synhronisers and time stamp counters spring to 
mind.
> The largest problem is just coming up with a chart recorder.  I have a couple of
> them and cannot find paper for them.  Standard office calculator/cash register
> paper is expensive enough, chart paper with holes on the side and a specific grid
> pattern is even worse.
>
>   
We have the opposite problem more chart paper and associated recorders 
than we currently have applications for.
> So, the way I see it, there are a number of people (Timenuts and Amateur radio
> operators via TAPR) who would probably be interested if it is not too involved.
> To handle those who are in the upper category, perhaps a second project aimed
> solely at them would also be appropriate.
>
>   
Yes I agree that a higher end system would be useful.
A modular approach would allow great flexibility.
The core component perhaps being a set (of 4?) high resolution ADCs like 
the AD7760.
This could be used for phase noise measurement  or for  measuring ADEV 
etc in a dual mixer setup.
> I am not dismissing your commentary, just noticing that it got way too involved
> too quickly.  Some of the stuff you were suggesting would involved some really
> serious work with programming not only the CPLDs or FPGAs (for which I have no
> knowledge) but much more effort dealing with the ADCs and such.  Well seems that
> way to me anyhow.
>
>   
I was attempting to provoke someone into producing some specifications 
for time stamp resolution etc.
100ns time stamp resolution is easily done using a counter a 
synchroniser and a time stamp register - easily fitted within a DIP 
compatible CPLD difficult (but not quite impossible if an appropriate 
micro is selected - eg some PICs can sample an internal counter on an 
external signal transition) with DIP packages or most micros.
With a higher frequency clock resolution to 10ns or so is also possible.
If single shot sub nanosecond resolution is required other techniques 
are more practical than using multi GHz clocks.
> Mainly I was really trying to get people to see that it should be a group
> effort.  Otherwise you have 3 or 4 people duplicating the wheel so to speak.  If
> those 3 or 4 could channel their efforts into one project perhaps we would end up
> with the best out of all 3 or 4.
>
> regards,
>
> Bill....WB6BNQ
>
>   
I agree duplication of effort is indeed wasteful.
Devising the best design possible within package, budget and other 
constraints is worthwhile.

Bruce