[time-nuts] Frequency Divider

[Hal Murray]

> JPL have used ECL dividers throughout to produce 10MHz, 1MHz and
> 100KHz outputs from the 100MHz signal derived from a Hydrogen maser:
> http://tmo.jpl.nasa.gov/progress_report2/42-30/30I.PDF 

We've been discussion converting sine to TTL.  JPL seems to be distributing 
ECL rather than sine.

This seems like more bait for a FAQ.

What are the (dis)advantages of using ECL or TTL vs sine for distribution?  
(I'm assuming "TTL" covers HC/AHC and 3V CMOS levels too.)

At the board level, digital designers often series terminate clocks.  There 
is no termination at the far end.  There is a resistor between the (low 
impedance) driver and the transmission line.   The lock goes out at half 
height and reflects off the far end.  The sum of the outgoing edge and the 
ref;ection give the input gate a clean full height signal.  The resistor back 
at the driver absorbs the reflection.  That works great for point-to-point 
links.  It's a disaster for clocks if you have multiple receivers along the 
transmission line since they see the signal at half height until the 
reflection gets back to them, a great opportunity for multiple clocking.

Does that work OK for distribution via coax?  If there is the classic 50 ohm 
to ground input termination the signal will only be half height.


What are the properties of various conversion approaches?
  how much noise/jitter is added?
    how much leaks through from the power supply?
  what is the phase drift with temperature?

I think the same questions are interesting for dividers using various 
technologies.  I think the simple divide by 2 with a FF covers all the 
different combinations of gates and FFs if you use a retiming FF at the end.


-- 
These are my opinions, not necessarily my employer's.  I hate spam.