[time-nuts] femtosecond jitter anyone?

[Bruce Griffiths]

Mike Monett wrote:
>   > Chris
>
>   > The biggest problem with the OCXO is probably that it has a square
>   > wave output.
>
>   > With careful  design it is possible to achieve a jitter  of  a few
>   > tens of femtosec for a logic level output from a limiter,  but the
>   > OCXO designers are unlikely to have used such a limiter.
>
>   [...]
>
>   > Bruce
>
>   Bruce
>
>   This would  be  an  excellent subject for  a  tutorial  on precision
>   system design. Do you have any links to support your claim of a tens
>   of femtosec for a logic level from a limiter?
>
>   I am  not  aware of any logic family that  can  support  that jitter
>   performance.
>
>   When you  post items that stretch the state of the art, it  would be
>   nice if you would show us all how to do the same.
>
>   Mike
>
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>   
Some ECL devices have jitter specs in the 100 to 200fsec range.
see:
http://www.onsemi.com



A jitter of a few tens of femtosec is achieved by some clock drivers:
http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/adclk905/products/product.html
http://www.analog.com/en/clock-and-timing/clock-generation-and-distribution/adclk925/products/product.html

Some ADC's have internal sampling jitter of a few tens of femtosec:
http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9461/products/product.html
However a very clean low noise source is required.


Achieving a jitter of less than a 1picosec at 10MHz with a well designed
limiter/filter cascade and a good source isn't too difficult, however
the intrinsic random jitter of most common logic families is indeed a
limiting factor.
(HCOS inverters have typical random jitter of ~ 4ps, ACMOS inverters
have an intrinsic random jitter of ~ 1ps faster CMOS families have lower
random jitter).
However such jitter can only be achieved if the logic gate input signal
slew rate is fast enough or the gates input noise will increase the jitter.

The achievable jitter increases as the input signal slew rate decreases
(ie a s the frequency decreases for a fixed amplitude sinewave input).

< 100ns jitter at 1Hz due to the limiter noise is routine (around 10ns
should be possible). JPL achieved < 100ns decades ago.
< 10ns jitter at 10Hz due to limiter noise is relatively easy whilst a
potential jitter of around 1ns rms is achievable.
However a clean low noise input signal is required.

Bruce