[time-nuts] PLL question

John Miles jmiles at pop.net
Mon Aug 10 14:10:50 UTC 2009


There is no need for a phase-frequency detector or any other steering
mechanism when the frequencies being locked never diverge by more than +/- 1
ppm.  Just use a diode mixer and active LPF, IMHO.

-- john, KE5FX

> -----Original Message-----
> From: time-nuts-bounces at febo.com [mailto:time-nuts-bounces at febo.com]On
> Behalf Of Magnus Danielson
> Sent: Monday, August 10, 2009 6:13 AM
> To: Discussion of precise time and frequency measurement
> Subject: Re: [time-nuts] PLL question
>
>
> >> ...I must admit, the tri-state PC did look good
> >> too until you pointed out the dead zone. I had assumed this
> >> would be insignificant, but of course it can't be. I'll still
> >> try the 74HC7046, but use the XOR PC instead.
> >
> > How about switching between the 4046's phase detectors, once the PLL has
> > locked?
>
> You can do that, the PFD lock detect could be used to let a CMOS analog
> gate switch over.
>
> > Or using a phase comparator like the AD9901 which has a "no
> dead zone" XOR
> > phase comparator coupled with a frequency comparator?
>
> Indeed, but too narrow pulses may still be a problem. The benefit of a
> continous signal is that the disturbance can be kept at a high frequency
> and thus be dampend out and the channel capacity for corrections is
> maintained high.
>
> > The later one can easily be put into a small cpld if you like.
>
> You can do alot of tricks in a CPLD. Getting the basic plot of what is
> good or bad system design still needs to be sorted out. Not meant as
> criticism, but just as a kind warning.
>
> Cheers,
> Magnus
>
>





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