[time-nuts] Best way for generating 8994.03 MHz from 2899.00042272.....MHz?

[Lux, Jim (337C)]

On 8/16/09 2:52 AM, "Javier Serrano" <javier.serrano.pareja at gmail.com>
wrote:

> Hi Hal,
> 
> I guess you are right. A DDS where I place a sine table spanning
> 2^20=1048576 locations will allow me to generate fout=fin*(step/2^20) but if
> I choose to use only 1000000 locations I can generate 1 kHz from 10 MHz
> exactly. Therefore this system would not need feedback. I have not looked at
> the details of how the DDS chips can be controlled, but there must be a way
> to tell them not to use the full RAM. So I guess then it boils down to a
> comparison between this DDS plus mixer based solution against Rick's
> solution (which IMO answers your question on how one builds a PLL at those
> frequencies).

The usual DDS chips (e.g. From Analog Devices) have a built in table of
fixed length.  If you want to use something other than the power of 2 it
comes with, you'll need to implement the NCO in an FPGA, with an external
DAC.

Depending on what your spur requirements are, although, you're lucky because
you don't need tunability, you might want to look at doing one of the
various forms of error compensation.

Watch out for aliasing of the harmonics of the output back into band. No DAC
is perfect, so you get some (unpredictable from the data sheet) harmonic
distortion of the output waveform.

The application notes from Analog Devices cover all this sort of thing, and
there are off-the-shelf free LogicCores, etc., from most of the FPGA vendors
for the building blocks.