[time-nuts] Best way for generating 8994.03 MHz from 2899.00042272.....MHz?

[John Miles]

>
> But I'm missing a couple of key ideas.
>
> How does one build a PLL at 3 GHz or 9 GHz?

I designed a board awhile back to try out some of the off-the-shelf PLL
chips from the same manufacturer: http://www.ke5fx.com/hpll.htm .  It's not
in the league that's being discussed here (although the JPL folks will find
the attempt amusing).

I like the performance of Hittite's parts, but they sure are power-hungry,
and the QFN packages they use aren't easy to solder at home.  If you don't
need unusually high reference (Fcomp) frequencies, the Analog Devices CMOS
parts are preferable IMHO just because they're easier to play with.

> Is there actually a 2998.01 clock?  If so, why is a simple 3x PLL not the
> right answer?
>
> Perhaps the true master clock is actually S-LO at
> 2998.01*732/757, and it's
> just written that way to make all the ratios visible for reasons that are
> important when you look at some other part of the problem.

These questions IMHO are exactly the right ones to ask, before speculating
on unconventional topologies and complicated block diagrams.  A birds'-eye
view of the overall conversion scheme would be helpful, assuming it's not
proprietary.

-- john, KE5FX