[time-nuts] Count up/down DAC circuit
SAIDJACK at aol.com
SAIDJACK at aol.com
Fri Jan 2 02:01:06 UTC 2009
Hi Steve,
not sure if the LPF would help, some issues with analog sample and holds
with long time-constants were recently discussed on this group. I am not a fan
of these to implement a GPSDO loop.
I guess it depends on your dac steps too. If you have a 16 bit dac over a 5V
EFC, then you have +/-32K steps, or 32K seconds to adjust.That's a very slow
slope.
Also, take into consideration that the GPS and the OCXO will "jump" over the
course of a typical day, and you need to track these jumps. Your tracking
speed may not be fast enough here.
Our best double-oven OCXO's still have ~+/-50 microvolt variations, and a
typical single oven may have +/-15mV variations over a 24 hour period. If you
don't have enough resolution, you will unnecessarily introduce quantization
noise, and if you do you would be lagging behind these natural changes.
What would probably work is if you over-sample the counter circuit to say
100x to 1000x (or in other words being able to take 100 to 1000 LSB steps per
second). That may prove to work out ok, and give you enough DAC resolution and
DAC speed.
With an M12+ set to 100PPS you may just make this work well enough! My gut
feeling is it won't work with 1PPS, but may work with 100PPS.
And if your DAC LSB step is very small, say 5E-013, then your tracking noise
would be quite small. Let's see, 100 steps per second, at 5E-13 per step
would give you a tracking speed of 5E-011 per second. That's probably good
enough.
A typical crystal jump of ~1E-09 would thus take only 20 seconds to correct.
Sounds reasonable to me. Note that this is a frequency locked loop rather
than a phase locked loop.
Let me know if you try it, and if you get it to work.
bye,
Said
In a message dated 12/30/2008 20:32:50 Pacific Standard Time,
sar10538 at gmail.com writes:
Hi Said,
Yes, I could see that my idea would suffer from this hunting in the
locked state problem an was wondering if this could be perhaps 'cured'
with a simple low-pass filter stage between the count up/down DAC and
the EFC, IE, the DAC would hunt up and down with a duty cycle equal to
the difference between the two DAC levels filtered by the LPF, thereby
giving a constant frequency.
This, of course, would further exasperate any problems trying to lock
a fast moving oxco or achieving lock in the first place. Some tuning
of the LPF time constant would be required to stop ringing as the PLL
moved into lock.
Do you think that would work as it would probably be easier to
implement than something to implement a dead-zone?
As for achieving lock in the first place with this idea, I'm thinking
now that it could take a very lon time for the DAC to count up/down
with output from a phase detector at 1PPS. I was really only thinking
about this whole idea as it seemed to be a natural to hold the EFC
voltage during lack of PPS if the GPS goes down. Without the PPS, the
phase detector will output no pulses so the DAC would remain frozen in
it's last state. Implementing a GPSDO via a phase detector followed by
a LPF would obviously be easier but in the absence of the PPS, I
imagine that leakage in the circuit would make the EFC voltage drift.
I guess I could buffer it with a source-follower or something like
that, or perhaps some form of sample and hokld circuit.
I was just bouncing around ideas as I know there are a lot of great
brains on this list.
73, Steve
2008/12/31 <SAIDJACK at aol.com>:
> Hi Steve,
>
> I played with such a circuit a long time ago.
>
> The slope is limited to the clocking of your circuit (one LSB digit per
> clock typ), which can present an issue if you cannot follow the OCXO's EFC
> changes fast enough. You could be chasing the OCXO voltage and this may
lead to
> instability.
>
> Even if it is "locked", the circuit will constantly be "chasing" the OCXO,
> unless you implement a dead-zone where the circuit stops counting up/down
when
> you are close enough to your target frequency.
>
> This chasing may cause the frequency to modulate up and down, and could
lead
> to large-scale oscillations.
>
> Tough to get this to work properly, but with circuitry to add a deadzone,
> and to dampen the lock, and maybe to introduce gain (jump more than one
LSB when
> far off etc) it may work. Then again implementing a standard PI controller
> (in a micro etc), and calculating it's stability etc is much easier than
> getting this to work properly.
>
> bye,
> Said
>
>
> In a message dated 12/29/2008 21:30:54 Pacific Standard Time,
> sar10538 at gmail.com writes:
>
> As part of the current idea I have with the hockey-pucks, I'm thinking
> about feeding the D1 and U1 phase difference pulses out of an MC4044
> out to some circuit that could clock up and down an analog output
> which would ultimately go to the EFC of a ocxo, IE D1 pulses when the
> phase of one input signal is advanced and visa versa for the U1 pin.
> Anyone seen a circuit like that please?
>
> Thanks & 73, Steve
> --
> Steve Rooke - ZL3TUV & G8KVD & JAKDTTNW
> Omnium finis imminet
>
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--
Steve Rooke - ZL3TUV & G8KVD & JAKDTTNW
Omnium finis imminet
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