[time-nuts] Z3805 initial behaviour after power up

Magnus Danielson magnus at rubidium.dyndns.org
Wed Jun 17 15:31:06 EDT 2009

Hi Brian,

Brian Kirby skrev:
> Ulrich,
> I have two Z3801A and both of them act close to what you describe in the 
> first 24 hours of power up.  I believe its part of the disciplining 
> algorithm.  From what I read about the smart clock, it takes 5 days for 
> it to complete its initial learning cycle and then its continuously 
> refining.

For me it sounds more like a design-flaw than anything else. Using 
several PLL bandwidths and switch between them is as such a good 
approach, but the stepping between then needs to be done such that a 
narrower bandwidth is only chosen when it the lock-in can be maintained. 
  Similarly, backing out of a narrow step to a wider step should also be 
detected at suitable levels when it can't maintain track. The phase 
detector gives hints about the ability to maintain track, as the phase 
will deviate uncontrollably when loosing lock, but before that happens 
it will deviate from near +/- 0 degrees, similarly, when within near +/- 
0 degrees for sufficient time it is reasnoble that the next step (if not 
too big) can maintain track. Recall that "sufficient time" changes with 
the bandwidth of the PLL.

A third degree (PII^2 or PII^2D) PLL is better able to cope with drift 
rate than a second degree PLL. A combined phase/frequency detection 
approach (I.e. add the D term) adds quicker response to drift and 
ability to keep tracking.

Another approach is to use a Kalman filter, where the Kalman gain is 
adapted continuously. Kalman filters takes some careful thought, it's 
not a magical wand to wave to make things better by magic. If done 
properly, it will be able to fairly well track along and detect the 
drift rate (takes a phase/frequency/drift model to handle) and update as 
it stabilizes.

None of these approaches is rocket science to design anymore. HP/Agilent 
surely could at the time of Z3801A and followers.


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