[time-nuts] GPSDO project - 66.667MHz from 10MHz

dave powis g4hup at btinternet.com
Sun Jun 28 18:15:44 EDT 2009


You can also use a DFS (Direct Frequency Synthesiser) to produce 66.667MHz in two ways - either 50 + 16.667MHz, or 70 - 3.33MHz. Information on the 50+16.667 is on my web site (http://g4hup.com), and has been implemented as a reference source for an SDR-IQ receiver.  Another customer of mine has also implemented the 70-3.33MHz version for the same application - I don't have the filter component values or detail design posted, but could provide them on request..

My personal preference is for the slightly more complex 50+16.667Mhz option, since the filtering is a little easier at VHF - but both solutions work, and give a good clean, stable low-noise output (depending on the quality of your 10MHz reference input, of course!)

Kits are available.

Hope this helps

73,
Dave, G4HUP




________________________________
From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
Sent: Sunday, 28 June, 2009 11:04:49 PM
Subject: Re: [time-nuts] GPSDO project

Hal Murray wrote:
> You want 66.6666 MHz from 10 MHz.
>
> I can think of several approaches.
>
> 1) Patch the radio stuff to work with 10 MHz.  Since 10 MHz is common from 
> things like GPSDOs or Telco surplus rubidium clocks, somebody may have done 
> that already.
>
> 2) Build a PLL.  The first step is probably to find a 66.666 MHz oscillator 
> that has an external fine tuning pin.  Then it's divide by 20 and 3, compare, 
> filter...
>
> 3) Get to 66.666 MHz by dividing by 3 then multiplying by 2 and 5.  I don't 
> know much about this area, but there was a lot of discussion here a few 
> months ago.  Check the archives.
>  

Actually need to multiply 3.333.. MHz by 20 (5 x 2 x 2)
No need to multiply by 2 or 4, if the output of the divide by 3 is a 1/3
duty cycle square wave, one can extract the 2nd (or 4th) harmonic of the
square wave repetition rate with a filter.
Amplify and multiply by 5 (can use the same approach as used in the
5370A/B frequency multiplier chain (1 transistor per multiplier) and filter.

A high level injection locked divider can have lower close in phase
noise than a digital one.

> 4) Use a DDS chip to synthesize 66.666 MHz.  Analog Devices makes lots of 
> nice ones.  One problem with DDSes is that they normally make spurs.  But 
> they aren't a problem if the target frequency is a clean multiple of the 
> source frequency.  20/3 doesn't sound clean, but I'd have to do a lot of work 
> to check the details.  There may be a clean frequency that is close enough to 
> 66.666 MHz and/or one that has spurs that are far enough out so you can 
> filter them.
>
> 5) Use a low cost 66.666 MHz oscillator and live with the error.  You may be 
> able to correct any errors.  The key step would be to feed the 66.666 MHz to 
> a counter running off the T-Bolt clock so you know the real frequency of your 
> 66.666 MHz osc.  Suppose your 66.666 MHz is 73 ppm fast and you want to 
> listen to 12.123 MHz.  You would set the radio to listen to 73 PPM below 
> 12.123 MHz.
>
>
>
>  

Bruce


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