[time-nuts] state of the art devide by ten
saidjack at aol.com
Mon Mar 30 00:54:00 EDT 2009
Wouldn't a Gray counter generate a nice stable sequence of switching
events for low jitter? Or how about a synchronous shift register set
up as a ring with a one going around in circles through the FF's?
On Mar 29, 2009, at 21:32, Bruce Griffiths
<bruce.griffiths at xtra.co.nz> wrote:
> Bill Janssen wrote:
>> I want to construct a divide by ten or a divide by 100 frequency
>> divider. This is to take my 10 MHz. from my
>> Rubidium to 1 MHz. or 100 KHz.
>> I could use the spare 74xx90 chips ( which I have) but I would like
>> make some thing useful for future
>> uses. What would be a "through the hole" type of IC that would have
>> jitter than a 74xx90. I CAN do
>> surface mount if I have to.
>> Bill K7NOM
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> If you want as low a jitter as is possible with a given logic family
> don't use a ripple carry (between the divide by 5 and divide by 2
> sections) device like a 74XX90. unless you use an external flipflop to
> resynchronise the divided output to the 10MHz clock.
> CMOS logic families like the 74AC can have a cycle to cycle jitter for
> an inverter clock buffer as low as 1ps. (Even HCMOS inverters can
> have a
> cycle to cycle jitter of around 4ps).
> However achieving this requires a suitable clock shaper and a low
> noise source.
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