[time-nuts] PIC Divider Performance (was Re: time-nuts Digest, Vol 56, Issue 71)
bruce.griffiths at xtra.co.nz
Mon Mar 30 21:33:26 EDT 2009
John Ackermann N8UR wrote:
> When Bruce raised the question a bit earlier, I was curious so set up a
> quick experiment.
> I happen to have two 10 MHz to 1 PPS dividers based on Tom's code. They
> lack the higher order outputs, so the modulation effects Bruce spoke of
> aren't present, but they should be a good test for general jitter. The
> circuit was simple -- the PIC output fed three paralleled 74AC04
> inverter gates, tied together through 47 ohm resistors on the output.
> So, the PIC itself was driving a high impedance load.
> I used a common 10 MHz signal to drive both dividers, and hooked their
> outputs to a 5370B TIC. Each divider ran from its own power supply, so
> there shouldn't have been any coupling that way.
> Over 1000 measurements at 1 PPS, I got a standard deviation of 46.9 ps.
> The delta between minimum and maximum readings was 330 ps. Since we
> were testing two independent dividers, I suppose you could divide the
> standard deviation by the square root of 2, which gives about 33 ps.
> I then did a test with a common PPS signal driving both inputs to the
> 5370B, with the stop signal run through a 4 meter cable for delay. This
> should show the noise floor of the TIC. The results for 1000 samples
> there were 23.0 ps standard deviation, and delta between min and max
> readings was 140 ps.
> Therefore, the PIC divider is a bit above the 5370B noise floor, but not
> (There is one point of caution in this comparison -- the noise floor
> test with coax delay line had an absolute time interval of about 18
> nanoseconds, while the interval between the two dividers was about 85
> milliseconds. In this quick test, I wasn't able to easily get the
> dividers in closer sync than that. With a longer time interval, the
> effects of TIC timebase might become more significant, and I suppose
> nonlinearities in the 5370B could also come into play.)
> And, for what it may further be worth, I did a very rough tempco
> measurement of another PIC divider and got about 50 ps/degree C over the
> range of +20 to +75 degrees C.
That delay tempco is consistent with ~ 12.5ns of internal CMOS clock to
output propagation delay.
An external flipflop with a shorter clock to output propagation delay
would have a lower delay tempco if the clock shaper/buffer delay also
has a low tempco.
> Bruce Griffiths said the following on 03/30/2009 08:09 PM:
>> Tom Van Baak wrote:
>>>> Probably the higher jitter and periodic phase modulation due to
>>>> simultaneous switching of multiple outputs at different frequencies.
>>>> The magnitude of the latter will depend on the loads driven by each output.
>>>> The cure is to use an external flipflop to resynchronise the outputs to
>>>> the 10Mhz clock.
>>> Kit, Bruce,
>>> There was no phase modulation effect that I could measure.
>>> Note that in that design all pins (a single 8-but IO port) are
>>> re-written each time through the loop; not just ones that change.
>>> See the source code for details.
>> But for example the 100KHz output pins actually only switch state every
>> 5th cycle of the 1MHz output.
>> This will modulate the phase of the 1MHz output at 100KHz due to ground
>> The magnitude of the modulation will depend on the load at the pins.
>> The higher the load capacitance (or lower the load resistance) the
>> greater the effect.
>> The effect will always be present, although whether you can detect it
>> depends on the resolution of the test setup and the pin load (C and R).
>> An SR620 is unlikely to have sufficient sensitivity for detecting the
>> effect with light pin loading.
>> In an FPGA with CMOS I/O such ground bounce and other coupling effects
>> can be a few tens of picosec even though the intrinsic jitter of the
>> internal logic elements is much smaller than this.
>> The PIC only has a single ground pin with a bonding wire inductance of a
>> few nH. If the outputs drive significant capacitance then the resultant
>> ground bounce can be significant.
>> An external flipflop can be connected so that it doesn't share the same
>> internal chip Vcc and GND wiring with outputs switching at different rates.
>> External ground plane noise can be much lower than internal chip GND net
>>> My understanding of the PIC architecture is that all outputs
>>> are essentially "resynchronized" to the clock by design. So
>>> that's why the PIC divider works so well. I can't see how an
>>> external off-chip flip-flop would be better than the existing
>>> internal on-chip flip-flop. Might even make things worse?
>> Only if one uses a slower external flipflop and/or a poor clock
>> buffering scheme.
>>> But I don't know for sure and should not guess. In cases like
>>> this I'd take an actual test over a random guess.
>>> As for jitter, I tested the PIC divider when I wrote it ten years
>>> ago and if I recall correctly the jitter was just over what I could
>>> measure with a SR620; about 25 ps. With better equipment
>>> these days, one could measure how much of that is input jitter,
>>> or output jitter, or measurement system jitter. But I don't have
>>> anything better than a 5370 or 620 for 1PPS measurements.
>>> I know the PIC divider was an order of magnitude better than
>>> other discrete 1PPS dividers that I had at the time, and it was
>>> 100x better than the reference 1PPS out of any GPS boards
>>> that I had, so I was very pleased with the performance (and
>>> the simplicity, and the cost) of the one-chip divider concept.
>> Almost anything reasonable is better than a cascade of 74XX90's with a
>> ripple cascade scheme between divide by 2 and divide by 5 sections.
>>> But it would be very interesting to me if someone with a working
>>> Wavecrest could make measurements of various PIC dividers
>>> and refine this old data; to find out just how low the noise floor is.
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