[time-nuts] On low-voltage TAC/TDCs for a GPSDO

[Bruce Griffiths]

J.D. Bakker wrote:
> At 23:49 +1200 14-08-2010, Bruce Griffiths wrote:
>> J.D. Bakker wrote:
>>> At 19:01 +1200 14-08-2010, Bruce Griffiths wrote:
>>>> J.D. Bakker wrote:
>> However the ultimate test (other than breadboarding it) is to 
>> actually simulate the sampling process and look at the deviation of 
>> the sampled voltages from linearity.
>
> That's not a bad idea (the recent "Simulation" thread 
> notwithstanding), I'll see if I can find the time to cobble something 
> together.
>
> Suggested procedure:
> - Assume perfect ADC buffers (not unrealistic, some of the MCP6xxx 
> parts have enough GBW and slew rate), and a 2V ADC reference.
> - Independent variables:
>   * Number of ADC bits (8...12)
>   * ADC input noise (model as AWGN, vary over 0...10LSB)
>   * ADC aperture jitter (AWGN, 0...2ns)
>   * ADC sample rate (1 or 2 MSPS)
>   * Ramp rate (0.1/0.2/0.5/1V/us, to be varied by changing C1 and only 
> C1)
>   * For Circuit 3: Difference between ramp rates (0...10%, again 
> through C1)
> - Have LTSpice generate a simulated ramp with enough time resolution 
> (say 100ps), do linear interpolation if needed.
> - For each combination of independent variables:
>   * Generate simulated ramp(s)
>   * Run a realistic number of -100ns/0ns/+100ns calibrations (call it 
> 100 runs)
>   * Sweep the simulated offset from -500ns to 500ns in 1ns steps
>   * For each simulated offset, do a few thousand measurement runs
>   * Collect statistics
> - Plot RMS and 90%-limits for the recorded data.
>
> That should keep all eight cores busy for a day or so. Does that sound 
> like a workable plan? If I feel up to it, I'll see if I can add the 
> simple RC-filter to the mix, although I'm less confident about doing 
> proper a priori weighed error curve fitting on that than on the simple 
> linear ramps.
>
Its probably more informative to look at the effect of the factors one 
at a time before doing the full blown simulation that includes all such 
factors.
Start with an ideal current source to isolate the effects due to switch 
capacitance etc, then try a few real current sources.

It should be a relatively simple case of a nonlinear least squares fit 
for the simple RC circuit.

Simulating the effect of statistical calibration using a uniformly 
distributed set of time intervals.
In this case the non linearity will be reflected in the non statistical 
variations in the histogram of frequencies for each ADC value.



> (I'd like to look at slower ramps/ADCs because the more I think about 
> it the more I prefer the ADuC7024, with +/-1LSB INL @1MSPS over the 
> +/-6LSB @2MSPS of the ATXMega. An added bonus of the ADuC is that it 
> has a small on-chip PLA, which might allow me to do without a CPLD).
>
>> In the case of the 3 diode TAC devised by Kasper Pedersen some 
>> compensation of diode capacitance modulation occurs if the diodes are 
>> matched.
>
> Hadn't seen that one yet. Looks interesting, but losing another two 
> diode drops on top of the current source's compliance range may be a 
> bit too tight for 3.3V operation.
>
>>> I've tried it in the simulator and on the bench, and it works quite 
>>> well.
>>
>> I'll check again, but thats not consistent with what I found with a 
>> simulated 1mA current source.
>
> As I mentioned a few messages ago the ramp becomes much more linear 
> (due to swamping of parasitics) when the current and the capacitor are 
> increased tenfold. Tried it again on the bench with the values as in 
> the attached sim file (SMD parts dead bug on a ground plane, with a 
> FDV301N in series with a 10R resistor shorting the capacitor, and a 
> resistor to set the current), and as far as I can eyeball it on my 
> 100MHz scope it works as advertised. Not that a scope check is the 
> last word in linearity, but at least there are no gross discrepancies 
> with the simulator's results. Having said that, I'm open for other 
> suggestions wrt the current source.
>
> JD "Monte Carlo" B.
>    
The deviations in the current visible in the simualtion are too small to 
be noticeable with a scope.
Increasing the ramp capacitor value has little effect on nonlinearity 
due to the Early effect.

Bruce