[time-nuts] Form Factor and such, Big Picture

[Bruce Griffiths]

A modern counter is usually based around multichannel high resolution 
time stamping.
To measure frequency one time stamps the output of a divider and 
combines these results with the number of unknown frequency periods 
between successive time stamps.
For example, one may divide down the reference (eg 10MHz) to produce the 
desired gate time.
This gate signal is then passed to a synchroniser clocked at the unknown 
frequency.
The output transitions of the synchroniser are time stamped whilst an 
auxiliary counter counts the number of periods of the unknown frequency 
between these transitions.
The counters dividers and synchronisers are best suited to 
implementation in an FPGA together with the coarse time stamping.
A set of time interval interpolators are used to measure the delay from 
the event to the next reference clock reference edge.

For higher frequencies a prescaler that divides the input signal 
frequency down to a frequency within the range of the main counter 
system implemented within the FPGA is required.

Input signal conditioning circuitry is also required to produce a logic 
level output for the main counter system.
A differential signal (eg LVDS or PECL) should be used to convey high 
frequency signals between such daughter boards and the main counter.

A processor of some kind to preprocess and format the data may also be 
required.

The main board should contain the FPGA, communications processor and 
(isolated?) comms interface to a PC

Daughter boards would consist of

1) Prescalers

2) Fine time interpolators (eg TAC)

3) Input signal conditioning

All of this should easily fit into a 1/2 width 2U sized enclosure.
Minimal communication with daughter boards other than setting input 
attenuators, gain and prescaler divisors should be required.
A simple means of determining such daughter card capabilities and 
presence may also be desirable.
The addition of serial EEPROM or equivalent may also be useful.

Timestamp noise on the order of 3-10ps should be easy to achieve 
provided that adequate layout techniques (eg ground plane an 4+ layer 
boards where required) are used.

Bruce