[time-nuts] CPLDs for clock dividers

Luis Cupido cupido at mail.ua.pt
Thu Feb 4 01:18:18 UTC 2010


Gerhard,

That is not by any means a CPLD. it is a big FPGA and I bet it would
be doing a bazilon things besides the divider.

Hummm... not really adds to the original question I'm afraid ;-)

Luis Cupido,
ct1dmk.


Gerhard Hoffmann wrote:
> I have done that with a Virtex4-SX on a ML402 board for fun and because 
> a customer insisted on it.
> It was a desaster on the spectrum analyzer. It will probably work if you 
> resynchronize the CPLD output with a 74LVC1G74 to the original clock.
> 
> 
> regards, Gerhard
> 
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