[time-nuts] Updated Shera controller

Bruce Griffiths bruce.griffiths at xtra.co.nz
Sat Jul 31 08:15:43 UTC 2010


Richard

Richard H McCorkle wrote:
> Bruce,
>
> Measurements were made to confirm the buffer settling time on two
> cascaded TS272 2x gain stages on a solderless breadboard using 10k
> resistors on first stage and 100k resistors with 2.5v offset
> correction on the second stage similar to the PICTIC II buffer
> arrangement. The buffer input was stepped using a 50 KHz logic
> waveform thru a divider to vary the input level. The input was
> used to trigger a dual channel scope and the delay from the input
> rise to the output peak and final settled value from the second
> buffer was measured at 500ns/div.
>    In all cases there was a delay before the waveform began to rise,
> a peak with a small overshoot, and 500ns later the output was stable
> at its final voltage. The pulse amplitude was varied over a 1.7v
> to 2.7v range similar to the data voltage range in the PICTIC II.
> The delay to peak varied from 1.7us to 2.4us with higher voltage
> inputs requiring longer times to output peak. In all cases the
> voltage settled to its final value 500ns after the output waveform
> peak, so worst case at the highest PICTIC II sample voltage the
> buffer output was stable 2.9us after the input rising edge. The
> 16F688 spec sheet recommends a maximum ADC input impedance of 10k
> ohms so the buffer is required.

Not true, you have to understand the context to which this 
recommendation applies: When sampling high frequency (several kHz) signals.
When sampling the output of a TAC a buffer isnt required when a low 
leakage input charge redistribution ADC is used.
One example of this is the TAC circuit (attached) taken from p22 of the 
LTC1273 (or p21 of the LTC1282) datasheet.
In these cases the effective source resistance is very low (a few tenths 
of an ohm at most due to the track resistance and external capacitor ESR).
One merely has to allow sufficient time for the charge to redistribute 
between the external TAC capacitor and the ADC sampling capacitance.
This will only be a few (<10) us for the 16F688 limited principally by 
the resistance of the sampling switch. On resistance nonlinearitiy in 
the sampling switch have no effect on the final value of the charge on 
the sampling capacitor and only have a small effect on the settling time 
of the charge on the sampling capacitor.

However if the ADC uses a resistive input multiplexer or attenuator as 
some do then a buffer is necessary.
Its also advisable to measure the actual leakage current on the analog 
input pin.
Typically for such ADCs (including those embedded within a 
microprocessor) its much lower than the datasheet limit which is largely 
determined by the testing cost.
Its much more expensive to test to tighter limits.


> It also recommends 4.7us between
> ADC channel select and conversion start to charge the channel input
> capacitance and combined with the interrupt overhead it will take
> approximately 10us to start the ADC read.
>
> Richard
>
>
Bruce
>> You can't predict the settling time of an opamp from its slew rate or
>> its gain-bandwidth product.
>> The TS272 datasheet has no settling time spec whatsoever.
>> In this case, since there is no spec it needs to be measured.
>> Opamps with 2 or more cascaded gain stages like these are notorious for
>> poor settling times.
>> 10us is merely guesswork.
>> The settling time could well be much longer and it may depend on the
>> input signal level.
>>
>> Bruce
>>
>>
>>
>> Richard H McCorkle wrote:
>>> FYI,
>>> The TS272/TS274 have a slew rate of 5.5v/us at unity gain, the max
>>> voltage on the cap is 2.7v in the new design, and the voltage is read
>>> <   10us after sample complete, so the buffer should have time to
>>> stabilize after the sample before being read.
>>>
>>> Richard
>>>
>>>
>>> Bruce wrote:
>>>
>>>> Not really its both overkill as it doesnt timestamp, it only 
>>>> measures a
>>>> time interval and underkill in that theres no DAC.
>>>> There are also some concerns about the settling time of the TAC buffer
>>>> opamp which isnt strictly necessary for the lower resolution 
>>>> required in
>>>> this application.
>>>> PPS timestamping only needs a single TAC.
>>>>
>>>> Bruce
>>>>
>>>>
>>>>
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>>>>
>>>
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>>
>>
>
>
>
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