[time-nuts] TPLL secret reveled
warrensjmail-one at yahoo.com
Thu Jun 10 19:16:34 EDT 2010
The ADC is measuring the EFC averaged voltage signal.
I think all understand that the EFC controls the Frequency of the Ref OSC.
This EFC voltage (freq) is what the external S/W uses to convert the two
oscillator differences into ADEV.
The Phase difference at the phase detector output is held to zero (within
1e-15 or so) by the gain of the AMP.
The phase detector output looks like a summing junction, nothing is going to
happen to make the point change from VERY nearly zero.
So there is NO phase change, because phase is always at a constant 90 deg
between the two oscillators.
sorry I can not explain it better than that, I'm sure other can.
> Fact #1) the TPLL uses Freq not phase,
Warren, can you please clarify. From what I can see it actually
uses a Minicircuits phase detector, right? That suggests what is
being observed is a phase difference between the DUT and the
REF, not a frequency difference.
That analog phase measurement is then filtered and amplified
into a pre-calibrated EFC correction to the REF which over a
short time reduces the phase difference as seen by the phase
detector. The digital stream comes from an ADC is connected
to the EFC.
So what does it mean to say "TPLL uses Freq not phase"? It
looks to me like it uses both.
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