[time-nuts] yet another GPSDO design, or so
Hal Murray
hmurray at megapathdsl.net
Tue Jun 29 18:39:43 UTC 2010
bruce.griffiths at xtra.co.nz said:
> Its possible to build a 24 bit resolution D/A using a synchronously
> filtered PWM circuit. A pair of PWM outputs and a few relatively low
> precision resistors and capacitors together with a low noise low drift
> reference are required. The technique takes advantage of the fact that the
> required EFC voltage changes slowly and isnt updated at a highg rate. The
> synchronous filter technique eliminates the very long time constant RC
> filters required with an asynchronously filtered PWM waveform.
24 bits is 16,777,216. At a reasonable clock rate, that's one second.
Another approach is to distribute the individual bits rather than clump them
together. If you want 1/2, send 10101010 rather than 11110000. You would
have to do something like build a bit pattern in memory and use a serial port
to send it out.
That shifts the frequency of the junk so that it's easier to filter out
and/or reduces the amplitude. If you send 10101010, you have lots of energy
but it's at 8 MHz. If you send 1000000, you have energy at 1 Hz, but it's
only 1/16000000 as big. Or something like that. [Since this is a linear
system, you will get that spur with any odd number of 1s.]
I can't determine if that's good enough. I think the math is similar to the
spurs you get from a DDS.
--
These are my opinions, not necessarily my employer's. I hate spam.
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