[time-nuts] Self-contained divider board/design available?

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Mar 12 20:49:00 UTC 2010


Bert


Bert, VE2ZAZ wrote:
> Hello Everyone,
>
> I warn you, this is a topic that has been discussed before...
>
> I enjoyed ko4bb's high level description of oscillator stability measurement (http://www.ko4bb.com/Timing/FAQ-1.php). Now I am looking into getting or putting together a self contained divider board that will allow me to make T.I. measurements at the PPS rate from a 10MHz reference using a HP 5370A counter. I am sure some of you have such boards. Are there any designs documented anywhere? Are there PCBs available?
>
> Otherwise, I have a tube full of 74AC163 sync. binary counters I believe could do the job. Intent was to put a cascade of 8 of these on a board. What recommendations would you give? I presume output re-timing is required with these devices since the TC output may have glitches, right?
Yes, the TC output may have glitches so it would need to be 
resynchronised if you use it.
Alternatively you could just use the Q3 (MS bit) output of the final AC163.
To divide by 1E7 you just need to preload the counters with an 
apprpriate value when TC on the last AC163 goes high.
You need to invert TC and use this signal to drive the synchronous 
preload of all the AC163's in the chain.
Alternatively you can configure each AC163 to divide by 10 by inverting 
its TC output and driving the synchronous load input with that signal.
The parallel inputs need to be wired to preload a 6 into the counter 
whenever the synchronous load goes low.


> Is a simple NPN transistor in common-emitter configuration good enough to buffer and scale the input signal, or should I go for a tuned input?
>
>    
Depends on the input signal level.
You may need to use schottky diode clamps to keep the transistor out of 
saturation.
If the signal is large enough you can drive a CMOS inverter directly (AC 
coupled).
Just dedicate a single chip for clock shaping don't share it with other 
signals.
> When it comes to performance, I understand there is quite a broad range of possible solutions, from the lousiest to the sharpest. My goal is to have a resonably good board that can deal with GPS-grade accuracy/stability. I don't intend to make atomic-level stability measurements (at least not for now, but who knows in the future...). ADEV measurement on GPS receivers, generators and oscillators is the objective.
>
>    
ACMOS has an intrinsic period jitter in the 1ps region, so the divider 
performance may depend more on the input signal characteristics.

> As you can see, this brings you back to basics. This is where I will start implementing T.I. measurements from...
>
> Thanks in advance,
>
> Bert.
> ps. please also reply direct, as I subscribe to Time-Nuts in the digest mode.
>
>
>
>    
Bruce





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