[time-nuts] Schematic and BOM

[Magnus Danielson]

Bob Camp wrote:
> Hi
>
> Good point, pretty much everything I worry about is timing to or from an external pin. Once it's "inside" it's all clocked to the global clock(s).
>   
If you look at the modern families, you no longer have "only" clocking 
on both edges... but even higher rates.

The I/O-block will clock in both directions. The trouble is when you 
want to do time-error for TIC designs, because you want to expose the 
edge-to-clock errors. To handle that, you want to steer that part of the 
logic to specific locations routing-wise near the pins, and naturally 
have selected pin-locations such that you achieve good internal routing. 
Keeping clear from other signals helps.

These are not hard things to do, you just need to think a little about 
it, apply common sense and find a way to achieve it in the tools.

If you have the wrong placement or design, you can get severe 
degradation as a result. I think one really has to fail to learn just 
what things are important and learn from that.

I will not say I am excelling at it, I have just a basic idea of timing, 
SI-issues etc. but it gives me a rough idea of where to start at least.

I should do some more FPGA projects. I have been way too lazy.

Cheers,
Magnus